ASIC Physical Design
1,421 open positions
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IC Design Engineer SilabsSingapore 2mo Designing digital circuits and integrating them into System-on-Chip (SoC) infrastructure for low-power wireless connectivity solutions.
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Senior RTL / Digital IC Design Engineer↗ Sparkgrid Pte. Ltd.Clementi, S00, SG 2mo Develop high-performance digital logic for Optical DSP (ODSP) and communication ASIC products, including RTL implementation, micro-architecture development, and silicon bring-up.
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Physical Design Implementation and STA Lead AlteraSan Jose, California, United States $149k–$149k2mo Lead physical design implementation and static timing analysis (STA) for next-generation FPGA SoCs, driving closure from floorplanning through signoff.
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Senior Engineer, RTL Design ArmBengaluru, India 2mo Designing complex compute subsystems and System-on-Chip (SoC) logic, integrating IP, and developing micro-architecture specifications.
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Staff Digital Design Engineer Renesas-ElectronicsChandler, Arizona, us 2mo Architecting, designing, and integrating low-power digital circuits for mixed-signal data conversion and power management products in advanced process nodes.
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Principal Hardware Engineer, AI Systems MicrosoftUnited States, Washington, Redmond 2mo End-to-end technical owner for next-generation AI and GPU platforms from architecture handoff through production deployment and fleet readiness.
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Sr. Staff Physical Design Timing Engineer (STA) LightmatterMountain View, CA $191k–$191k2mo Drive backend digital execution and timing closure for leading-edge silicon photonics chips in extreme-scale data centers.
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Automotive High-Speed Hardware Design Engineer Bosch-GroupBengaluru, in 2mo Lead hardware design and development for ADAS, Cockpit, and Connectivity ECUs, focusing on high-speed digital boards and sensor integration.
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Principal ASIC Design Engine NxpHyderabad 2mo Designing and implementing complex digital blocks and subsystems for next-generation AI inference accelerators and SoCs.
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Senior ASIC Timing Engineer NVIDIAUS, CA, Santa Clara $136k–$136k2mo Lead timing analysis and closure for NVIDIA GPUs, CPUs, LPUs, and SoCs at block, cluster, and full chip levels.
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Lead FPGA Design Engineer JabilAustin, TX 2mo Leading FPGA design, development, integration, and debug for complex server, storage, networking, and AI infrastructure platforms.
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Senior STA Engineer MediaTekAustin, TX 2mo Senior STA Engineer responsible for timing sign-off, constraint development, and margin methodology for mobile CPU blocks in next-generation SoCs.
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ASIC Implementation Engineer STA BroadcomUSA-CA San Jose Innovation Drive $144k–$144k2mo Ensuring ASIC meets performance targets and timing requirements across all operating conditions via full-chip static timing analysis (STA) and sign-off.
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Design Engineer II CadenceHYDERABAD 2mo Developing, automating, and maintaining EDA flows and scripts for physical implementation of IP cores and soft controllers to optimize performance and power.
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Sr. RTL Design Engineer (Silicon Engineering) SpaceXAustin - 800 $165k–$165k2mo Developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures to enable global connectivity via the Starlink network.
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Principal Engineer, Digital IC Design and Architecture AnalogdevicesUS, OR, Beaverton $157k–$157k2mo Architect and design digital blocks and subsystems for high-speed SerDes ICs, driving next-gen automotive connectivity standards and enabling data transport for autonomous driving and digital cockpits.
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System Architect for Advanced Memory System Architecture- DMTS/SMTS MicronBengaluru, India 2mo Designing next-generation memory and storage subsystem architectures for AI, servers, and mobile systems, optimizing power and performance through system-level simulation and modeling.
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Digital IC Design Engineer (INT TRX) Texas InstrumentsDallas, TX, United States 2mo Architect and design high-performance digital circuits interfacing with analog systems for automotive and industrial applications.
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SOC Architect - Chiplet TenstorrentRemote 2mo Architecting the central compute chiplet for next-generation automotive SoCs, translating safety requirements into high-performance silicon designs.
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