Senior Engineer, RTL Design
Core
Designing complex compute subsystems and System-on-Chip (SoC) logic, integrating IP, and developing micro-architecture specifications.
Role type
Senior RTL Design Engineer
Builds
SoC logic and subsystems for compute platforms
Domain
Semiconductor / SoC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Verilog HDL, digital hardware design, SoC development techniques, design specification creation, RTL development, scripting (Perl/Python)
Preferred skills
ARM-based designs, PCIe/LPDDR/HBM/UCIe/Ethernet integration, SystemVerilog, UVM/OVM verification, synthesis and timing analysis, static design checks (CDC/RDC/X-Propagation), power management, DFT
Technologies
Verilog, SystemVerilog, UVM, OVM, Perl, Python, ARM, PCIe, LPDDR, HBM, UCIe, Ethernet
Responsibilities
Integrate IP and develop logic for SoCs; write micro-architecture specifications; develop RTL and run design checks; review test plans with verification team; evaluate subsystem performance; enhance design methodologies; guide and support team members; collaborate on project plans and schedules
Seniority
Senior, hands-on IC
