ASIC Physical Design
1,421 open positions
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Digital Physical Design Engineer NxpNoida 2mo Drive timing closure, fix setup/hold violations, and optimize designs for performance and area using Synthesis, Place & Route (PnR), and Static Timing Analysis (STA).
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Sr. Physical Design Engineer LumilensSan Jose 2mo Senior Physical Design Engineer owning full-chip and block-level physical implementation from RTL to GDSII for high-performance ASICs in advanced TSMC nodes (5nm/3nm).
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Principal SSD Systems Design Engineer MicronLongmont, Colorado, United States of America 2mo Lead system-level design, architecture definition, and multi-domain technical resolution for Solid State Drive (SSD) products from concept to manufacturing.
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Product Engineer - Physical Design Siemens-EdaBangalore, IND, India 2mo Develop flow and methodology for placement, clock tree synthesis (CTS), and routing on advanced process nodes (7nm and 5nm) using Aprisa tools to help customers achieve performance, area, and power targets.
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ASIC Architect CerebrasHeadquarters/Sunnyvale Office 2mo Designing and optimizing the micro-architecture of the world's largest AI chip to enable ultra-high-speed training and inference for AI workloads.
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Principal ASIC Chip Design Engineer NVIDIAIsrael, Tel Aviv 2mo Establish ASIC design methodologies, develop shared code, and drive adoption of new technologies to ensure efficient chip design operations.
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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) SpaceXAustin - 800 $175k–$175k2mo Developing cutting-edge next-generation silicon for deployment in space and ground infrastructures to enable global connectivity via the Starlink network.
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Senior Performance Architect MicrosoftUnited States, Oregon, Hillsboro 2mo Develop performance modeling methodologies and analysis tools for System on Chip (SOC) and Intellectual Property (IP) to identify bottlenecks and justify architectural changes.
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Senior Digital Engineer Renesas-ElectronicsChandler, Arizona, us 2mo Architect, design, and integrate low-power digital circuits for mixed-signal data conversion and power management products in advanced process nodes.
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Spécialiste FPGA - Aéronautique (F/H) AltenBordeaux, Nouvelle-Aquitaine, fr 2mo Develop and validate complex FPGA/SOC designs for critical embedded aerospace applications (video systems, flight computers, energy management) ensuring reliability and DO254 compliance.
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Senior Physical Design Engineer Cisco2 Locations 2mo Lead backend VLSI design flow development from RTL to GDS, handling definition, physical synthesis, place and route, optimization, timing closure, and floor planning for high-quality ASIC designs.
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Director, Silicon Design Engineering IntelUS, California, Santa Clara $221k–$312k2mo Physical Design Timing Engineer ensuring optimal timing, power efficiency, and performance for Intel's next-generation System-on-Chip (SoC) products.
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ASIC Digital Design, Architect↗ Synopsys IncDublin, County Dublin, Ireland 2mo Leading the design and verification of complex ASIC blocks and systems to ensure they meet specifications and performance goals.
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Senior Engineer-STA ArmBengaluru, India 2mo Developing and validating timing constraints and performing timing analysis/closure for System-on-Chip (SoC) and block/subsystem levels.
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Staff Engineer, Physical Design SifiveBengaluru, Karnataka, India 2mo Drive end-to-end physical design implementation (Synthesis, Floorplanning, P&R, Signoff) for next-generation IPs, translating complex RTL into high-performance silicon while optimizing Power, Performance, and Area (PPA).
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Principal Engineer, Digital Design (IO Subsystem) ON SemiconductorAllen, TX, United States 2mo Architecting and delivering a highly configurable IO subsystem for onsemi's microcontroller platform to enable scalability and product differentiation.
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ASIC SoC System Architect, Lund AxisSweden - Lund 2mo Define system-level architecture and requirements for ARTPEC SoC chips, selecting third-party IPs and collaborating with RTL design, verification, and ASIC vendor teams to deliver security features for IoT ecosystems.
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Director, Silicon Logical Design GraphcoreBristol 2mo Lead and scale the Logical Design group to define micro-architecture and RTL for Graphcore's AI compute chips, ensuring world-class performance, power, area, and schedule.
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Senior Hardware Design Engineer, Ethernet Switching Arista-NetworksRoseville, CA, us $162k–$162k2mo Designing high-speed Ethernet switching hardware for AI clusters, data centers, and enterprise campuses.
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High Speed Interface Protocols, Principal AE CadenceSAN JOSE $123k–$123k2mo Architect high-speed interface solutions for customers using Cadence Serdes IP and showcase performance to win business opportunities.
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Technical Leader Physical Design
AmazonTel Aviv-Yafo, Tel Aviv, Israel
2mo
Leading physical design development for advanced semiconductor nodes, optimizing power, area, and performance for cloud computing infrastructure.
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Physical Design Technical Lead AlteraSan Jose, California, United States $210k–$210k2mo Own complex SOC and block-level implementation challenges end-to-end, from floorplan and power intent through final signoff, while shaping ML/AI-driven implementation flows.
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Chip Design Engineer, Nitro Team
AmazonTel Aviv-Yafo, Tel Aviv, Israel
2mo
Design and develop micro-architecture and RTL for the AWS Nitro SoC, integrating into millions of servers worldwide.
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Career Accelerator Program - Digital Design Engineer Texas InstrumentsTucson, AZ, United States 2mo Architect new TI products by defining, designing, modeling, and verifying digital circuits including 64-bit DSP processors, MMUs, and multicore shared memory systems.
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DFx Engineer Samsung Electronics3900 N Capital of Texas Hwy, Austin, TX, USA $180k–$180k2mo Architecting and implementing Design for Test (DFT) scan solutions for high-performance digital IP (CPU/GPU) and System-on-Chip (SoC) projects to ensure high test coverage and yield.
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Physical Design Engineer
AmazonTel Aviv-Yafo, Tel Aviv, Israel
2mo
Developing semiconductor platforms and next-generation cloud products using revolutionary system architectures.
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Logic Lead FlirIndia - Pune 2mo Architectural design and FPGA implementation of next-generation wireless protocol analyzers to capture, demodulate, and process high-speed RF signals.
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Architecture ASIC Engineer MarvellCordoba, Argentina 2mo Design, simulate, and validate DSP ASICs for coherent optical communications systems serving Data Center interconnect and Long Haul/Metro markets.
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Senior Member of the Technical Staff GlobalFoundriesHsinchu 2mo Senior technical leadership role driving the development and delivery of high-performance compute processor IP solutions.
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