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Hardware & Physical Engineering
› ASIC Physical Design
ASIC Physical Design
1,341 open positions
Principal ASIC Design Engine
Nxp
Hyderabad
2mo
Designing and implementing complex digital blocks and subsystems for next-generation AI inference accelerators and SoCs.
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Senior ASIC Timing Engineer
NVIDIA
US, CA, Santa Clara
$136k–$136k
2mo
Lead timing analysis and closure for NVIDIA GPUs, CPUs, LPUs, and SoCs at block, cluster, and full chip levels.
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ASIC Implementation Engineer STA
Broadcom
USA-CA San Jose Innovation Drive
$144k–$144k
2mo
Ensuring ASIC meets performance targets and timing requirements across all operating conditions via full-chip static timing analysis (STA) and sign-off.
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Design Engineer II
Cadence
HYDERABAD
2mo
Developing, automating, and maintaining EDA flows and scripts for physical implementation of IP cores and soft controllers to optimize performance and power.
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Associate Staff/Staff Implementation Design Engineer
Silabs
Singapore
2mo
Leading and hands-on execution of backend (BE) implementation flow for high-performance SoCs and ASICs, ensuring timing closure and PPA optimization.
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Senior RTL Design Engineer
Arm
Bristol, United Kingdom
2mo
Designing sophisticated micro-architecture and RTL for innovative IPs used in Physical AI, Automotive, Edge, and Infrastructure computing.
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Principal Hardware ASIC Architect engineer
Nxp
Hyderabad
2mo
Define and own architecture for compute, memory, interconnect, and high-speed interface subsystems in AI inference chips, balancing performance, power, and area (PPA) from concept through silicon.
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RTL Design Engineer (Silicon Engineering)
SpaceX
Irvine, CA
$125k–$125k
2mo
Designing next-generation FPGAs and ASICs for Starlink satellite and ground infrastructure to enable global broadband connectivity.
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Sr. RTL Design Engineer (Silicon Engineering)
SpaceX
Austin - 800
$165k–$165k
2mo
Developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures to enable global connectivity via the Starlink network.
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Principal Platform Power and Performance Engineer
Microsoft
United States, Washington, Redmond
2mo
Lead technical strategy and optimization for silicon and platform power-performance architecture, focusing on AI infrastructure, datacenter efficiency, and workload characterization.
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System Architect for Advanced Memory System Architecture- DMTS/SMTS
Micron
Bengaluru, India
2mo
Designing next-generation memory and storage subsystem architectures for AI, servers, and mobile systems, optimizing power and performance through system-level simulation and modeling.
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Engineer, Firmware Design
Micron
Hyderabad - Phoenix Aquila, India
2mo
Design and validation of on-chip controller and mixed signal circuitry in NAND FLASH chips.
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Staff SSD Hardware PCIe Engineer
Micron
Boise, ID - Main Site
$138k–$138k
2mo
Developing modern SSD controller technologies and implementing high-impact solutions for performance and reliability.
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ASIC Design Engineer
NVIDIA
US, CA, Santa Clara
$116k–$190k
2mo
Designing high-performance, power-efficient RTL for SoC and GPU products including microarchitecture, IPs, and system components.
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Principal Engineer, Digital IC Design and Architecture
Analogdevices
US, OR, Beaverton
$157k–$157k
2mo
Architect and design digital blocks and subsystems for high-speed SerDes ICs, driving next-gen automotive connectivity standards and enabling data transport for autonomous driving and digital cockpits.
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Principal NoC IP Micro-Architect
Altera
San Jose, California, United States
$210k–$210k
2mo
Designing and leading the end-to-end architecture, microarchitecture, and RTL development of scalable Network-on-Chip (NoC) IP solutions for next-generation FPGA platforms.
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Digital IC Design Engineer (INT TRX)
Texas Instruments
Dallas, TX, United States
2mo
Architect and design high-performance digital circuits interfacing with analog systems for automotive and industrial applications.
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Principal Engineer
Arm
Bengaluru, India
2mo
Design and test new hardware modules to implement innovative imaging algorithms and video codecs for Image Signal Processors (ISPs), Display Processors, and Video codecs within Arm Compute Subsystems.
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Principal FPGA Engineer (f/m/d)
Nxp
Hamburg, DE
2mo
Define and advance FPGA strategy, methodologies, and design flows while developing FPGA-based prototyping platforms for mobile payment and security solutions.
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Firmware Design Engineer
Cadence
MOUNT-ROYAL (Montreal), CA
$74k–$137k
2mo
Developing physical IP for industry-standard high-speed serial-link protocols, specifically firmware for SERDES PHYs.
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Physical Design Engineer
NVIDIA
Israel, Tel Aviv
2mo
Designing and implementing advanced hardware solutions for next-generation AI and computing platforms, focusing on high-speed digital build and signal integrity.
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Senior ASIC Design Engineer
NVIDIA
US, CA, Santa Clara
$168k–$168k
2mo
Implement, document, and deliver high-performance, area, and power-efficient RTL for NVIDIA's leading SoCs and GPUs, focusing on micro-architecture, scheduling, and interconnects.
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Senior Engineer, Digital Design Engineer
Analogdevices
US, MA, Wilmington
$117k–$117k
2mo
Lead methodology improvements for physical design flows across complex chip and SoC programs to enhance scalability, reuse, efficiency, and predictability.
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Chiplet Design Architect
Tenstorrent
Remote
$100k–$100k
2mo
Define architecture for next-generation chiplet-based compute platforms enabling high-performance RISC-V CPUs within scalable System-in-Package (SiP) solutions.
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DFT Engineer
Tenstorrent
Remote
$100k–$100k
2mo
Design and integrate multiple chiplets into a System-in-package for high-speed CPU core designs.
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SOC Architect - Chiplet
Tenstorrent
Remote
2mo
Architecting the central compute chiplet for next-generation automotive SoCs, translating safety requirements into high-performance silicon designs.
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Physical Design Engineer - STA
Tenstorrent
Austin
$100k–$100k
2mo
Drive static timing analysis (STA) and closure for complex, high-performance RISC-V CPUs and AI SoCs to meet aggressive performance goals.
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Chiplet Physical Design Engineer
Tenstorrent
Remote
$100k–$100k
2mo
Designing and integrating multiple chiplets into a System-in-Package (SiP) for high-performance CPU and AI silicon.
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Top Level Physical Design Engineer
Tenstorrent
Austin
$100k–$100k
2mo
Senior-level Physical Design Engineer driving top-level implementation of complex AI and CPU System-on-Chip designs, orchestrating cross-disciplinary collaboration for floorplans, power grids, and clock networks.
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AI/ML Physical Design Flow Engineer
Tenstorrent
Austin
$100k–$100k
2mo
Architecting and deploying AI/ML-driven solutions into production physical design flows to improve PPA and runtime on advanced semiconductor nodes.
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Engineering Program Manager, RISCV
Tenstorrent
Santa Clara
$100k–$100k
2mo
Leading the full lifecycle of a high-performance RISC-V CPU from specification to tapeout and post-silicon debug.
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Sr. Engineer, CPU RTL Design
Tenstorrent
Santa Clara
$100k–$100k
2mo
Designing and implementing RTL for high-performance RISC-V CPU blocks, focusing on microarchitecture definition and optimization.
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Senior DFT Engineer, Architecture
Tenstorrent
Tokyo
2mo
Design and integrate multiple chiplets into a System-in-package and implement DFT for high-speed CPU core design.
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Staff Engineer, Physical Design
Tenstorrent
Austin
$100k–$100k
2mo
Implement high-performance blocks for industry-leading CPU and AI/ML architectures, owning the complete implementation flow from synthesis to tapeout.
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Physical Design Engineer, PnR
Tenstorrent
Santa Clara
$100k–$100k
2mo
Implement high-performance partitions for an industry-leading AI SOC, owning the complete implementation flow from synthesis to tapeout.
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Sr Staff Engineer, SoC RTL Design
Tenstorrent
Boston
2mo
Define, build, and optimize high-performance IP and SoC architectures for next-gen AI and compute workloads.
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Physical Design Engineer: Die-to-Die Interface (RTL to GDSII)
Tenstorrent
Remote
$100k–$100k
2mo
Drive Die-to-Die (D2D) physical implementation from RTL to GDSII for multi-die/chiplet architectures in high-performance AI chips.
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Principal CPU Microarchitect - RISC-V & AI Compute
Tenstorrent
Austin
2mo
Designing high-performance RISC-V CPU cores and custom instruction set extensions to address bottlenecks in modern AI workloads, specifically Large Language Models (LLMs).
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Principal Physical Design Engineer
Microsoft
United States, California, Mountain View
2mo
Lead and execute Physical Design activities at block, sub-chip, and full-chip levels, driving implementation phases from floorplanning to signoff.
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Principal SoC Circuit Architect
Microsoft
United States, California, Mountain View
2mo
Define high-speed IO PHYs (Ethernet, HBM4/4E/5), signal/power integrity, and end-to-end power delivery solutions for SoCs.
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Sr EDA Engineer
Renesas-Electronics
Remote
2mo
Maintain, support, and enhance production RTL-to-Gates implementation, static verification, and signoff flows for digital backend projects.
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FPGA Design Engineer
Philips
Haifa
2mo
Develop, design, and optimize FPGA solutions for detection projects in CT/AMI, focusing on digital design and system integration.
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Principal, IC Digital Design Engineer
Marvell
Irvine, CA
$151k–$223k
2mo
Design high-performance digital ASICs for next-generation Ethernet and optical interconnects powering AI data centers, focusing on high-speed datapaths, DSP pipelines, and protocol handling.
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Principal Product Engineer
Cadence
BANGALORE
2mo
Develop and maintain digital reference flows for ASIC implementation, including synthesis, floorplanning, timing closure, and PPA optimization for advanced process nodes.
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R&D FPGA Developer in HVDC MACH
Hitachi
Krakow, Lesser Poland, Poland
2mo
Design, implement, and validate FPGA-based control and protection systems for High Voltage Direct Current (HVDC) stations, specifically the Modular Advanced Control for HVDC (MACH™) platform.
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<Data center>Digital IC Design Engineer_Taipei (SOC BE w/ AI)
MediaTek
Taipei
2mo
Improving digital IC design flow and methodology using AI, executing EDA tasks for synthesis, timing analysis, and netlist quality control, and optimizing PPA with AI or EDA tools.
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Applications Engineer
Arm
Austin, Texas
$130k–$130k
2mo
Provide technical mentorship on IP integration, configuration, and performance to Arm's partners building SoC designs integrating Arm CPUs and System IP.
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Physical Design Engineer
Nxp
Pune
2mo
Execute block-level physical design implementation for complex SoC/IP blocks in advanced technology nodes, ensuring PPA and reliability standards.
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Staff Digital Systems Engineer
Moog
Phoenix, AZ
$185k–$185k
2mo
Architect, design, integrate, and verify complex FPGA-, ASIC-, and processor-based digital hardware for high-reliability aerospace and defense systems.
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FPGA Lead Engineer
MediaTek
HsinChu
2mo
Lead FPGA development activities including functional prototyping, emulation, performance evaluation, and database generation flows.
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