Staff Physical Design Engineer
Core
Implementing complex digital blocks for high-performance ASICs in advanced process nodes (3nm), focusing on timing closure, power integrity, and physical verification for photonics engines.
Role type
Senior IC physical design engineer (ASIC)
Builds
3nm ASICs and photonics engines for AI/HPC data centers
Domain
Semiconductor manufacturing / Photonics / AI Infrastructure
Deliverable
production ML models | product features | infrastructure
Required skills
Physical design flow (synthesis to signoff), timing closure, power grid design, DRC/LVS closure, TCL/Python scripting, advanced process node knowledge (3nm)
Preferred skills
Cadence tools, tape-out experience at 3nm, silicon photonics layout
Technologies
Cadence, TCL, Python, Shell
Responsibilities
Implement digital blocks from synthesis through physical verification; debug timing constraints and fix violations; build and customize power grids; customize clock implementation; debug DRC/LVS; write automation scripts
Seniority
Senior, hands-on IC