Principal Engineer, Digital IC Design and Architecture
Core
Architect and design digital blocks and subsystems for high-speed SerDes ICs, driving next-gen automotive connectivity standards and enabling data transport for autonomous driving and digital cockpits.
Role type
Principal Engineer, Digital IC Design and Architecture
Builds
High-speed SerDes ICs and OpenGMSL connectivity solutions for automotive, industrial, and medical applications
Domain
Semiconductor / Automotive Electronics / High-Speed Digital Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Digital architecture and design, Verilog/SystemVerilog, SerDes transceiver architectures, timing analysis, power estimation, physical design, DFT concepts, silicon bring-up and debug, system-level planning
Preferred skills
High-speed SerDes standards (Ethernet, USB, PCIe, DisplayPort, CSI/DSI, HDMI), behavioral modeling, DSP design (Matlab, digital filters), team leadership
Technologies
Verilog, SystemVerilog, Matlab, OpenGMSL, SerDes
Responsibilities
Architect and design digital blocks and subsystems of complex high-speed SerDes ICs; Drive evolution of OpenGMSL technology and author technical standards; Write detailed block and subsystem-level specifications; Design digital blocks and top-level designs using RTL; Develop testbenches and collaborate on full-chip verification; Perform linting, CDC analysis, and power analysis; Communicate with mixed-signal teams for simulations; Prepare technical documentation and lead design reviews; Support silicon bring-up, characterization, and debug; Provide technical leadership for complex SerDes subsystems
Seniority
Principal, hands-on IC design with strategic standards leadership
