Sr. Engineer, CPU RTL Design
Core
Designing and implementing RTL for high-performance RISC-V CPU blocks, focusing on microarchitecture definition and optimization.
Role type
Senior IC CPU RTL Design Engineer
Builds
High-performance RISC-V CPU cores
Domain
Semiconductor / CPU Design / RISC-V
Deliverable
production ML models
Required skills
CPU microarchitecture expertise, RTL coding (Verilog/VHDL), simulation and synthesis tools, debugging across design hierarchies, performance-driven trade-off analysis
Preferred skills
Experience with Rename, Scheduler, ROB, Load Store, Branch Prediction, Cache, or Datapath
Technologies
Verilog, VHDL, industry-standard simulation and synthesis tools
Responsibilities
Own RTL design and microarchitecture development for a portion of a CPU block, collaborate with DV, PD, and performance engineers to meet functional, timing, and power goals, optimize power, performance, and area through RTL experiments, partner with validation and test teams for robust execution, enhance RTL design environment and tools
Seniority
Senior, hands-on IC
