Senior Engineer, Digital Design Engineer
Core
Lead methodology improvements for physical design flows across complex chip and SoC programs to enhance scalability, reuse, efficiency, and predictability.
Role type
Senior IC physical design methodology engineer
Builds
Scalable, reusable, and efficient physical design implementation flows for complex SoCs
Domain
Semiconductor physical design and SoC implementation
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (physical design flows)
Required skills
Physical design fundamentals (floorplanning, placement, CTS, routing, timing closure), EDA tool expertise, scripting (Tcl/Python), systematic root cause analysis, cross-functional collaboration, technical trade-off judgment
Preferred skills
Advanced-node SoC implementation experience, AI/automation in engineering workflows, Synopsys or Cadence tool proficiency
Technologies
Tcl, Python, Synopsys, Cadence
Responsibilities
Drive physical design flow standardization and automation; Define guardrails and best practices for implementation teams; Analyze QoR (power, performance, area, timing) to identify flow gaps; Debug recurring implementation and convergence issues; Provide technical guidance on methodology adoption; Support critical flow troubleshooting and validation
Seniority
Senior, hands-on IC with methodology leadership focus
