Senior Engineer, Digital Design Engineer
Core
Lead methodology improvements for physical design flows across complex chip and SoC programs to enhance scalability, reuse, efficiency, and predictability.
Role type
Senior Physical Design Methodology Engineer
Builds
Scalable, reusable physical design implementation flows and automation scripts for complex SoC programs
Domain
Semiconductor / Physical Design / EDA
Required skills
Physical design fundamentals (floorplanning, placement, CTS, routing, timing closure), EDA tool expertise, scripting (Tcl/Python), flow automation, root cause analysis, cross-functional collaboration
Preferred skills
Advanced-node SoC experience, AI/automation in engineering workflows, Synopsys or Cadence tools
Technologies
Tcl, Python, Synopsys, Cadence
Responsibilities
Drive physical design flow standardization and automation, define best practices and guardrails, analyze QoR outcomes, debug implementation issues, provide technical guidance to design teams
Seniority
Senior, hands-on IC with methodology leadership
