Principal Physical Design Engineer
Core
Leading physical design implementation and integration for cutting-edge semiconductor products at block, subsystem, sub-chip, and full-chip levels.
Role type
Principal Physical Design Engineer
Builds
Complex ASICs in leading edge technology
Domain
Semiconductor / VLSI Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> physical/clinical work (Note: Correcting to 'physical design implementation' based on context, but the label options are fixed. The prompt says 'physical/clinical work' is an option. This is a physical design role. I will map it to the closest valid option or omit if none fit perfectly. Actually, looking at the options: 'production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work'. None of these perfectly describe 'Physical Design Implementation' except perhaps 'infrastructure' (flow development) or 'product features' (the chip itself). However, the instruction says 'Extract only facts stated explicitly... do NOT infer'. The text says 'Physical Design tasks'. I will use 'product features' as the chip is the product, or 'infrastructure' for the flow. Let's look closer. 'Physical Design implementation' creates the product. I will select 'product features' as the chip is the feature/product being built. Wait, the prompt examples are specific. Let's re-read the options. 'physical/clinical work' is for things like manufacturing or medical. This is design. I will omit if no fit, but 'product features' is the best fit for building a chip. Actually, the prompt says 'Deliverable: <one of: ...>'. I must choose one. The role builds the chip. I will choose 'product features'.)
Required skills
Floorplanning, Synthesis, Placement, CTS, custom clocking, Routing, Static Timing, Physical Verification, Formal Equivalency, Power Efficiency, IR-Drop, EM analysis, Physical Design flow development/automation, Technology/IP/vendor selection
Preferred skills
Leading team to deliver planned goals, Driving PD team at SOC level, Working with limited direction
Technologies
Leading edge technology, Complex ASICs
Responsibilities
Execute physical design implementation and integration at block/subsystem/sub-chip/full-chip levels, Perform floorplanning, synthesis, placement, CTS, routing, static timing, and physical verification, Drive PD team to set and deliver quality results per milestone goals, Evaluate and recommend technology, IP, and vendor selection, Provide status of progress, issues, and risks to management
Seniority
Principal, hands-on IC with team leadership
