Principal High-Speed I/O Architect (PCIe, CXL, UA Link)
Core
Design and define innovative on-chip interconnect architectures (coherent and non-coherent) for scalable SoC platforms across mobile, automotive, datacenter, networking, and IoT markets.
Role type
Principal High-Speed I/O Architect
Builds
Production-quality silicon with top-tier performance and efficiency for next-generation SoCs
Domain
Semiconductor architecture, high-speed I/O protocols, SoC design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
coherency protocols, hierarchical cache design, PCIe/CXL/UA Link protocols, link-level behavior, transaction flows, ordering models, memory expansion/pooling, die-to-die connectivity, chiplet connectivity, heterogeneous compute, security, caching, memory systems
Preferred skills
strategic project delivery, dynamic environment adaptability
Technologies
PCIe, CXL, UA Link
Responsibilities
Architect high-speed interconnect subsystems and define communication architectures; Define IP and subsystem roadmaps for high-speed I/O; Lead early architecture engagements with customers to shape system requirements; Collaborate with performance, power, and physical design teams to optimize subsystem behavior; Develop SoC architecture integrating Arm IP and high-speed I/O subsystems; Partner with software, firmware, and platform teams to optimize end-to-end solutions; Support detailed use-case exploration, workload analysis, and performance modeling
Seniority
Principal, strategy & mentorship