ASIC Verification Engineering
1,776 open positions
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CPU IP Design & Verification Intern – RISC-V Processor Development (Summer 2027) GlobalFoundriesUSA - California - Santa Clara today Design and verification of advanced RISC-V processor IP, focusing on microarchitecture, RTL implementation, and functional verification.
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Emulation Verification Engineer (Japan Design Center) AppleMinato, Japan today Utilizing emulation for verification of large Display and Wireless SoCs, including porting designs to the Palladium platform and executing test plans.
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FY27 Intern - Design For Test for a Secure Asynchronous IP - 6 months, Montbonnot QualcommMontbonnot, France 1d Improve test capabilities of a Secure Enclave IP (TESIC) for System-on-Chips, focusing on Memory Build-In Self-Test (MBIST), Design for Test (DFT), test coverage, and fault analysis within a security context.
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Staff Analog Mix Signal FPGA Engineer (f/m/div) InfineonMunich 1d Drive FPGA-based modeling for mixed-signal IPs and comprehensive system platforms, bridging hardware and software to enable early firmware validation and architecture exploration.
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Lead Digital Design Engineer AnalogdevicesIreland, Limerick 1d Architect and design complex digital blocks and subsystems for high-performance Automatic Test Equipment (ATE) solutions used in production testing of microprocessors and EV battery modules.
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Senior Digital Verification Engineer CadenceCESSON SEVIGNE 01, FR 1d Lead the development and execution of robust, reusable UVM verification environments for high-performance ASIC designs, ensuring functional coverage and first-silicon success.
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Senior Engineer↗ eTeamDublin, County Dublin, Ireland 1d Verification of full Rx and Tx chains for an ongoing chip design, including simulation, compliance reporting, and register control validation.
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ASIC DFT Engineer BroadcomUSA-CA San Jose Innovation Drive $144k1d ASIC DFT Engineer responsible for SoC DFT implementation, verification, debug, and post-silicon bring-up activities.
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FPGA Design Verification Intern AlteraToronto, Ontario, Canada CA$95k–CA$100k1d Verifying Altera IPs such as PCIe, Ethernet, Search, and DR, including hardware debug/bring-up and regression triaging.
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SoC Design Verification Engineer IntelUS, California, Santa Clara $106k–$149k1d Perform functional logic verification of Intel's next-generation Xeon server SoCs to ensure accuracy, reliability, and performance for global data center markets.
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Staff Verification Engineer ArmBengaluru, India 1d Staff Verification Engineer responsible for verifying functional correctness of Subsystems and SoCs for Enterprise, Auto, and Client markets.
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Engineer, CPU Performance Verification TenstorrentAustin $100k–$500k1d Drive performance verification and correlation between RTL and performance models for a high-performance RISC-V CPU.
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Principal Design Verification Engineer (AI Fabric Switches) AsteralabsSan Jose $185k–$240k2d Functional verification of complex ASICs for rack-scale AI infrastructure, focusing on connectivity solutions like CXL, Ethernet, NVLink, and PCIe.
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QA/Test Engineer Siemens-EdaNew Cairo, EGY, Egypt $18k2d Develop and execute test plans, design test cases, and build automation frameworks for Electronic Design Automation (EDA) software and hardware verification solutions.
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Design Verification Manager↗ Omnivision 2d Lead a verification team to develop and deploy state-of-the-art verification methodologies for complex SoC designs, achieving zero-defects.
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DFT Implementation Lead EliyanUSA $177k–$217k3d Lead the design, implementation, and validation of DFT IP and features for advanced packaging (2.5D/3DIC) and chiplet-based systems, ensuring high yield and quality for ATE and in-system testing.
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SMTS Silicon Design Engineer Advanced Micro Devices, IncAustin, Texas 3d Lead research group for emerging formal verification domains (security, safety, low-power) and steer technical roadmap for formalizing ISA and memory model for GFXIP design.
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FPGA Verification Engineer (Entry Level) Sopra-SteriaPlatteville, WI, us 3d Verification of real-time embedded FPGA systems for aerospace and defense applications, ensuring compliance with DO-254 objectives.
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Senior Digital Design Verification Engineer - Hardware NVIDIAUS, CA, Santa Clara 4d Verify design and implementation of cutting-edge SerDes IPs to enable gaming, AI, deep learning, and autonomous driving.
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Physical Verification Engineer (12 Months Contract)↗ PersolSingapore, S00, SG 4d Full-chip Physical Verification Sign-off covering DRC, LVS, ANT, ERC, ESD, and PERC for tape-out.
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DFT Engineer↗ Arete Resources Pte. Ltd.Yishun, S00, SG 4d Design-for-Test (DFT) engineer responsible for implementing and verifying DFT solutions for complex hierarchical SoC/ASIC designs to ensure first-pass silicon success.
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ASIC DFT Engineer I (Full Time) - United States CiscoSan Jose, California, US $95k–$157k4d Implement Hardware Design-for-Test (DFT) features to support ATE, in-system test, debug, and diagnostics for Cisco's core Switching, Routing, and Wireless products.
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