Sr. RTL Design Engineer (Silicon Engineering)
Core
Developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures to enable global connectivity via the Starlink network.
Role type
Senior IC RTL Design Engineer (ASIC)
Builds
Next-generation ASICs for Starlink satellites and ground infrastructure
Domain
Aerospace / Satellite Communications / Hardware Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL implementation in Verilog/System Verilog, micro-architecture definition, timing closure, silicon bring-up and validation, clock domain crossing, power optimization, embedded CPU subsystems, standard bus protocols (AXI, AHB), EDA tools (HDL simulators, Lint), Python scripting
Preferred skills
ASIC/SoC system integration, high speed and low power design techniques
Technologies
Verilog, System Verilog, Python, AXI, AHB, EDA tools
Responsibilities
Evaluate architectural trade-offs based on features, performance requirements and system limitations; Define micro-architecture and implement RTL; Integrate RTL into top level and deliver fully verified, synthesis/timing clean design; Work closely with verification team to ensure design coverage; Provide timing constraints for IPs and support physical implementation team; Participate in silicon bring-up and validation
Seniority
Senior, hands-on IC
