Principal ASIC Design Engine
Core
Designing and implementing complex digital blocks and subsystems for next-generation AI inference accelerators and SoCs.
Role type
Principal ASIC Design Engineer (Digital Design)
Builds
AI inference SoCs, custom ISA-based processors, high-speed interconnects, and high-bandwidth I/O
Domain
Semiconductor / AI Hardware Acceleration
Deliverable
production ML models
Required skills
RTL design (System Verilog/Verilog), micro-architecture development, synthesis, timing analysis, power optimization, clock/reset architecture, low-power design techniques, lint/CDC/RDC flows, debugging and root-cause analysis
Preferred skills
Experience with AI inference workloads, performance bottleneck analysis, collaboration with physical design and verification teams
Technologies
System Verilog, Verilog, AI inference frameworks
Responsibilities
Define and implement hardware architectures optimized for AI inference SoCs; Contribute to microarchitecture definition and evaluate design trade-offs for complex SoCs; Own features end to end from specification through synthesis and debug; Collaborate with physical design teams on timing closure and power optimization; Work with verification teams to ensure design correctness; Partner with architecture engineers to model workloads and validate AI inference use cases
Seniority
Principal, hands-on IC
