ASIC Implementation Engineer STA
Core
Ensuring ASIC meets performance targets and timing requirements across all operating conditions via full-chip static timing analysis (STA) and sign-off.
Role type
Senior IC ASIC Implementation Engineer (STA)
Builds
ASIC chips meeting timing closure for production
Domain
Semiconductor / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Full-chip timing sign-off, SDC constraint development, On-Chip Variation (AOCV/POCV) analysis, Signal Integrity (crosstalk) analysis, IR-drop aware STA, Multi-Mode Multi-Corner (MMMC) analysis, Timing ECO generation, Tcl scripting, Python scripting, Perl scripting, Cross-functional collaboration with RTL/Physical Design/DFT teams, Power/performance/area tradeoff analysis
Preferred skills
Expert proficiency in industry-standard sign-off tools (Cadence or Synopsys), Experience managing on-chip variation derates, Optimizing multi-mode multi-corner constraints
Technologies
Cadence, Synopsys, Tcl, Python, Perl, Shell
Responsibilities
Own final timing closure for ASIC, Author and validate SDC for functional and test modes, Incorporate foundry guidelines into timing analysis flows, Analyze hundreds of timing scenarios for reliability, Automate ECOs to fix timing violations, Partner with cross-functional teams to resolve timing issues, Document best practices for continuous improvement
Seniority
Senior, hands-on IC
