ASIC Physical Design
1,421 open positions
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Physical Design Engineer - STA TenstorrentAustin $100k–$100k2mo Drive static timing analysis (STA) and closure for complex, high-performance RISC-V CPUs and AI SoCs to meet aggressive performance goals.
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Principal Physical Design Engineer MicrosoftUnited States, California, Mountain View 2mo Lead and execute Physical Design activities at block, sub-chip, and full-chip levels, driving implementation phases from floorplanning to signoff.
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Sr EDA Engineer Renesas-ElectronicsRemote 2mo Maintain, support, and enhance production RTL-to-Gates implementation, static verification, and signoff flows for digital backend projects.
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Senior ASIC Design Engineer NVIDIAUS, CA, Santa Clara $136k–$136k2mo Design and implement world-leading GPU and SoC architectures, including system-level modules like Reset and Boot controllers, for applications ranging from consumer graphics to self-driving cars and AI.
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Principal, IC Digital Design Engineer MarvellIrvine, CA $151k–$223k2mo Design high-performance digital ASICs for next-generation Ethernet and optical interconnects powering AI data centers, focusing on high-speed datapaths, DSP pipelines, and protocol handling.
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R&D FPGA Developer in HVDC MACH HitachiKrakow, Lesser Poland, Poland 2mo Design, implement, and validate FPGA-based control and protection systems for High Voltage Direct Current (HVDC) stations, specifically the Modular Advanced Control for HVDC (MACH™) platform.
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Applications Engineer ArmAustin, Texas $130k–$130k2mo Provide technical mentorship on IP integration, configuration, and performance to Arm's partners building SoC designs integrating Arm CPUs and System IP.
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Physical Design Engineer- CPU/GPU MediaTekBangalore 2mo Responsible for RTL to GDS design and development of ARM/Imagination-based graphics processors, AI processors, and neural network DSPs.
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Staff Digital Systems Engineer MoogPhoenix, AZ $185k–$185k2mo Architect, design, integrate, and verify complex FPGA-, ASIC-, and processor-based digital hardware for high-reliability aerospace and defense systems.
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Principal Hardware Engineer, SSD MicronBoise, ID - Main Site $164k–$164k2mo Design and develop next-generation Solid State Drive (SSD) hardware architectures for data centers, AI infrastructure, and client computing.
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Physical Design Engineer NxpPune 2mo Execute block-level physical design implementation for complex SoC/IP blocks in advanced technology nodes, ensuring PPA and reliability standards.
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FPGA Design Engineer PhilipsHaifa 2mo Develop, design, and optimize FPGA solutions for detection projects in CT/AMI, focusing on digital design and system integration.
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Principal Engineer - Standard Cell Design IntelUS, California, Santa Clara $221k–$312k2mo Define next-generation standard cell library architecture, DTCO, and design methodology to deliver high-performance, low-voltage silicon for CPU, GPU, and emerging architectures.
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SOC Timing Engineer AlteraPenang 15, Penang, Malaysia 2mo Responsible for timing closure and signoff of FPGA/SoC and Subsystem timing, including static timing analysis and deriving interface timing constraints.
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Principal Product Engineer CadenceBANGALORE 2mo Develop and maintain digital reference flows for ASIC implementation, including synthesis, floorplanning, timing closure, and PPA optimization for advanced process nodes.
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Senior Engineer BroadcomIND-Bangalore Electronic City - S1, IN 2mo Senior Engineer leading physical design activities for SOC chips, covering floor-planning, placement, routing, verification, and timing closure.
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Senior Firmware Engineer, FPGA CoreWeaveBellevue, WA $182k–$182k2mo Design, implement, validate, and maintain FPGA-based platform functionality for server-class AI compute platforms, ensuring clean integration with BMC firmware, BIOS, and hardware.
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Staff Silicon Product Engineer WaymoTaipei (TW-TPE-101) $5200k–$5200k2mo Architect and create high-performance custom silicon and system-level compute architectures for Waymo's fully autonomous vehicle software stack.
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Ingénieur Spécialiste Electronique Hardware FPGA / ASIC - F/H AltenToulouse, Occitanie, fr 2mo Senior hardware specialist providing high-level expertise in FPGA/ASIC design, embedded software, and electronic circuit validation for aerospace/defense clients.
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Staff / Senior Staff CAD & Methodology Engineer (Digital Implementation & Signoff) Enchargeai36India 2mo Architecting and optimizing automated RTL-to-GDSII physical design and timing signoff flows for AI accelerator architectures.
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Product Engineer - Physical Design Siemens-EdaBangalore, IND, India 2mo Develop flow and methodology for placement, clock tree synthesis (CTS), and routing on advanced process nodes (7nm and 5nm) using Aprisa tools to help customers achieve performance, area, and power targets.
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Technical Program Manager, Hardware Chips Development OpenAISan Francisco 2mo Managing the design and implementation planning of ML acceleration hardware and chip hardware roadmaps for OpenAI's supercomputers.
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