RTL Design Engineer (Silicon Engineering)
Core
Designing next-generation FPGAs and ASICs for Starlink satellite and ground infrastructure to enable global broadband connectivity.
Role type
RTL Design Engineer (Silicon Engineering)
Builds
FPGAs and ASICs for Starlink satellites and user terminals
Domain
Aerospace / Satellite Communications / Hardware Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL Design (SystemVerilog, Verilog, VHDL), ASIC/FPGA design lifecycle, high-level architectural design, cross-functional collaboration, electrical engineering fundamentals
Preferred skills
Python scripting, DSP/digital communication datapath design, EDA tools (HDL simulators), AXI/AHB/APB protocols, Master's degree in EE/CS
Technologies
SystemVerilog, Verilog, VHDL, Python, EDA tools, AXI, AHB, APB
Responsibilities
Design ASICs and/or FPGAs implementing IP for complex SoCs, participate in full ASIC/FPGA design lifecycle from architecture to validation, engage in high-level architectural design, collaborate on new technologies for User terminals and Satellites
Seniority
Mid-level IC Engineer