Principal Engineer
Core
Design and test new hardware modules to implement innovative imaging algorithms and video codecs for Image Signal Processors (ISPs), Display Processors, and Video codecs within Arm Compute Subsystems.
Role type
Principal ASIC RTL Design Engineer (Multimedia IP)
Builds
Image Signal Processors (ISPs), Display Processors, and Video codecs
Domain
Semiconductor / Hardware Design / Multimedia IP
Deliverable
production ML models
Required skills
ASIC RTL design, System Verilog, Verilog, VHDL, architectural modeling, backend implementation support, UNIX scripting (TCL, Perl, Python, shell), technical leadership
Preferred skills
advanced image processing algorithms (tone mapping, noise reduction, motion estimation), AI/ML computer vision, Functional Safety (ISO 26262, IEC 61508), MATLAB, C, C++, SystemVerilog Assertions (SVA), Continuous Integration flows
Technologies
AMBA interfaces, DDR specifications
Responsibilities
Ownership of unit level development or multiple unit hierarchy, Design and test new hardware modules, Engage in all aspects of hardware design including architectural investigations and modeling, Identify cross Media IP process or methodology improvement opportunities, Collaborate with verification, modeling, software driver, and research teams, Mentor and support other team members
Seniority
Principal, technical leadership & mentorship