ASIC Implementation Engineer PD
Core
ASIC top level floorplan Physical Design Engineer responsible for taking RTL to silicon tape-out for AI and PCIe Switch products.
Role type
Senior IC ASIC Physical Design Engineer
Builds
Next generation Artificial Intelligence and PCIe Switch chips
Domain
Semiconductor / ASIC Physical Design
Deliverable
production ML models | product features
Required skills
Chip floor planning, partition creation, clock tree synthesis, bump planning, RDL implementation, multi-voltage domain design, hierarchical floorplanning, power grid design, structured clocks, top level pipeline planning, custom routes, DRC/LVS/EMIR resolution, scripting (Python/Tcl/Perl), EDA tools
Preferred skills
Die size estimation, pin planning, vendor/IP evaluation, cross-functional collaboration with package teams
Technologies
Switch Fabric, Arbiter, High Speed DDR, SerDes, HBM, D2D I/O, chiplet, Python, Tcl, Perl
Responsibilities
Own chip floor planning and partition creation, resolve physical design issues related to chip integration and assembly, manage cross functional interactions with package team, develop floorplan implementation methodologies, perform technical evaluations of vendors and IP
Seniority
Senior, hands-on IC