ASIC Physical Design

1,415 open positions

ASIC/SOC Silicon Physical Design Engineer MatXMountain View (HQ) or Remote $160k–$160k2y Developing performant and functionally correct silicon for high-performance and sustainable GenAI across compute, memory management, and high-speed connectivity.
Lead Application Engineer - GCS ( Physical Design ) CadenceBANGALORE 2y Lead Application Engineer providing post-sales technical consultation, debugging, and implementation guidance for digital and sign-off EDA tools to global customers.
Physical Design Engineer MediaTekHsinChu 2y Implementing 7nm to 3nm chip designs, focusing on physical design methodology and sign-off.
Digital IC Engineer_Zhubei MediaTekChuPei 2y Design and integrate digital System-on-Chip (SoC) architectures, covering floorplanning, RTL design, synthesis, implementation, and verification for complex SoC/IP blocks.
<Automotive>SOC clock architect MediaTekHsinChu 3y Develop scalable platform clocking architecture for automotive SoCs, optimizing power, performance, and implementation.
<Automotive>Memory System Architect / Designer MediaTekHsinChu 3y Develop and implement tailored DRAM controller/PHY solutions and system-level cache strategies for automotive applications, ensuring compliance with industry standards.
Digital IC Designer MediaTekHsinChu 3y Architecture design and RTL implementation of Smartphone chipset and SoC system performance analysis.
Sr. Digital Implementation Engineer AlifsemiIrvine, CA 3y Creating turn-key solutions for Cellular IoT devices by owning netlist delivery to Physical Design and ensuring RTL database integrity.
SOC Low Power Architect MediaTekHsinChu 4y Define SoC low power architecture and optimize power states to maximize battery life and user experience.
<Automotive>Smart Cockpit and Smartphone SoC Digital IC Design Engineer MediaTekHsinChu 4y Architecture design and RTL implementation of Automotive/Smartphone chipsets, including system power, performance, bus, memory, low power, functional safety, and cyber security analysis.
SOC System Architect MediaTekHsinChu 7y Define and optimize SOC hardware architecture and associated software flows to improve system performance, power efficiency, and area.
Physical Design Engineer Squircle-It-Consulting-Services-Pvt-LtdBengaluru, KA, in $0k–$0k10y IC Physical Design Implementation for high-utilization, congestion, and timing-driven blocks.
Director of Analog Design – Wearable SoCs (On-site. West Lafayette, USA) IxanaWest Lafayette, IN $175k–$175k Architect next-generation Wi-R SoCs integrating analog/RF front-end, ultra-low-power digital blocks, and sensor interfaces for brain-inspired wearable computing.
RTL Design & Integration Engineer (On-site. Bengaluru, India) IxanaBengaluru, India Integrate internal and external IPs into top-level System-on-Chips (SoCs) for ultra-low-power, brain-inspired wearable compute systems.
Senior RTL Design Engineer (On-site. Bengaluru, India) IxanaBengaluru, India Architect and design ultra-low-power digital systems and control/data path blocks for next-gen wearables using patented Wi-R technology.

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