Engineering Program Manager, RISCV
Core
Leading the full lifecycle of a high-performance RISC-V CPU from specification to tapeout and post-silicon debug.
Role type
Engineering Program Manager for CPU development
Builds
High-performance RISC-V CPU IP
Domain
Semiconductor / CPU Architecture / Silicon Development
Deliverable
production ML models
Required skills
CPU/SoC/silicon development experience, cross-functional team alignment, scope/schedule/resource definition, risk management, Functional Safety (ISO 26262) knowledge
Preferred skills
Automotive industry standards experience
Technologies
RISC-V, DFT, Verification, Physical Design
Responsibilities
Define scope, schedule, and resources for CPU programs; lead execution across architecture, design, verification, and DFT teams; drive silicon development milestones; manage risk and report metrics to leadership
Seniority
Open to various levels (entry to senior)
