ASIC Physical Design
1,421 open positions
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ASIC Engineer, Design↗ MetaAustin, TX, US $146k–$146k2mo Design and optimize low-power hardware accelerators, SoCs, and custom silicon solutions for machine learning, graphics, display, and network acceleration.
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Senior Chip Design Engineer NVIDIAIsrael, Tel Aviv 2mo Design and implement next-generation Switch Silicon chips for high-speed communication devices, focusing on throughput and latency.
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ASIC Engineering Technical Leader CiscoTaipei, Taiwan 2mo Define, design, and verify high-performance ASICs and subsystems for Cisco networking platforms (routers, switches, optical), focusing on power, performance, and area goals.
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Senior DRAM RTL design engineer MicronHyderabad - Phoenix Aquila, India 2mo Design digital IP blocks for DRAM memory solutions from microarchitecture to RTL, covering full-chip integration, verification, and layout.
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Campus ASIC Engineer (Intern) JumptradingBristol 2mo Design, test, and bring up custom ASIC hardware for ultra-low-latency trading systems using machine learning and algorithms.
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Sr. Formal Verification Engineer, Annapurna Labs
AmazonAustin, Texas, United States
$159k–$159k2mo
Design and optimize hardware for cloud-scale machine learning acceleration, specifically focusing on IP architectures for products like AWS Inferentia.
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Silicon Domain Architect AlteraSan Jose, California, United States $119k–$119k2mo Define and develop next-generation FPGA silicon architecture, focusing on security technologies, Root of Trust, and hardware/software integration.
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Sr. Staff Physical Design Engineer LightmatterMountain View, CA $217k–$217k2mo Implement complex digital blocks for high-performance ASICs in advanced process nodes (3nm), driving timing closure, power integrity, and physical verification for photonics engines.
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DFT (Design For Test) Lead (6251) ItdRemote 2mo Lead the implementation and integration of advanced Design-for-Test (DFT) solutions across the silicon development lifecycle to ensure highly testable, manufacturable, and reliable ASIC designs.
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Senior Silicon Engineer MicrosoftUnited States, Washington, Redmond $120k–$120k2mo Lead capture and validation of design intent for digital and mixed-signal blocks, ensuring accurate constraints and seamless integration across front-end and physical design flows.
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Principal /Sr. Staff PD Implementation Expert Renesas-ElectronicsBengaluru, KA, in 2mo Drive the complete RTL-to-GDSII physical design flow for next-generation, high-performance System-on-Chips (SoCs), focusing on aggressive Power, Performance, and Area (PPA) metrics.
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Graduate Talent (Physical Design Engineer) IntelMalaysia, Penang 2mo Graduate Physical Design Engineer developing reference designs using Intel Foundational IP and ensuring quality through SoC design flow execution.
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Staff Engineer: STA Methodology & Sign-off Lead Enchargeai36India 2mo Architect and lead Static Timing Analysis (STA) methodology and sign-off architecture for large-scale System-on-Chip (SOC) designs to ensure timing convergence and eliminate bottlenecks.
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Hardware Engineer Intern - Summer 2027 ImcChicago $200k–$200k2mo 10-week summer internship focusing on hardware design, algorithm complexity, and RTL programming within a financial trading firm.
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Senior Engineer, Digital Design Engineering AnalogdevicesSpain, Valencia, Cortes Valencianas 2mo Senior Digital Design Engineer responsible for FPGA prototyping, RTL design, and architectural specification of complex SoC blocks for the Intelligent Edge.
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Physical Design Engineer - Flow & Methodologies EtchedSan Jose 2mo Architect and maintain automated RTL-to-GDSII physical design flows from first principles to enable rapid iteration and PPA gains for frontier AI inference clusters.
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ASIC Senior Principal Engineer : Design Veirifcation HpeBengaluru, Karnātaka, India 2mo Leads a team of ICs and project teams in the full lifecycle of VLSI design, validation, and testing for complex products and platforms.
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R&D Engineer BroadcomIND-Bangalore Electronic City - S1 2mo R&D Engineer responsible for physical design, place and route, timing closure, and tapeout integrity checks for top-level-route chips.
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Hardware Development Engineer GraphcoreBristol 2mo Design circuit solutions and validation platforms for Graphcore AI processor systems, turning system requirements into schematics, layouts, and testable hardware.
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ASIC Digital Design Expert (f/m/div) Bosch-GroupRemote 2mo Design digital circuits for advanced Mixed-Signal and System-on-Chip (SoC) ASICs driving leading-edge consumer applications, focusing on MEMS sensor integrated circuits.
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Memory Design Engineer AmbiqmicroincSingapore 2mo Design and validate ultra-low-power embedded SRAM and Register File IPs for advanced SoCs operating in sub-threshold and near-threshold voltage ranges.
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Lead Design Engineer CadenceCARY, US 2mo Implement, verify, and achieve timing closure for high-performance hardware-assisted verification SOCs (Palladium and Protium) to support tape-out.
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