Physical Design Engineer, PnR
Core
Implement high-performance partitions for an industry-leading AI SOC, owning the complete implementation flow from synthesis to tapeout.
Role type
Physical Design Engineer (PnR)
Builds
High-performance AI System-on-Chip (SoC) partitions
Domain
Semiconductor / AI Hardware / Physical Design
Deliverable
production ML models
Required skills
Synthesis, Place-and-Route (PNR), Static Timing Analysis (STA), Synopsys Design Compiler, Synopsys Fusion Compiler, Synopsys IC Compiler II, UPF, SoC interface IP integration, DRC/LVS, EM/IR, LEC, Formality, Multi-clock/CDC-aware implementation, PLL/DLL integration, DFT-aware physical implementation
Preferred skills
Experience with complex AI SoC flows, analog/mixed-signal macro integration, DFT features (OCC/MBIST)
Technologies
Synopsys Design Compiler, Synopsys Fusion Compiler, Synopsys IC Compiler II, UPF, I3C, UART, OCC, MBIST
Responsibilities
Execute synthesis, PNR, and STA for assigned partitions of a complex AI SoC; Help close EM/IR and ensure UPF power intent consistency; Drive LEC and physical verification signoff; Work with architects, RTL designers, and DFT engineers to resolve implementation issues
Seniority
Mid-level to Senior IC Engineer