ASIC Physical Design
1,415 open positions
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Sr Staff Digital Engineer Renesas-ElectronicsDuluth, GEORGIA, us today Architect and design RTL in Verilog for mixed-signal integrated circuits, overseeing digital backend design including synthesis, static timing analysis, and logic equivalence checking.
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Bluespec Design Engineer (Haskell)
MatXMountain View (HQ) or Remote
$160k–$160k1d
Designing performant silicon RTL at the full-chip or subsystem level for high-performance and sustainable GenAI using Bluespec.
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Senior Hardware Engineer - PCB Design HpeBengaluru, Karnātaka, India 1d Lead the development of next-generation routing and switching platforms from concept to production, focusing on high-speed board design, system-level problem solving, and bringing up complex electronic systems.
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AI/ML Logic Design Engineer Senior QualcommUSA $134k–$134k1d Senior IC logic design engineer developing microarchitecture and RTL for next-generation Hexagon NPU to power AI/ML applications.
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Staff Engineer, ASIC STA MicronBengaluru, India 2d Staff Engineer leading Static Timing Analysis (STA), Synthesis, and Logic Equivalence Checking (LEC) for complex mixed-signal ASIC designs in memory and storage solutions.
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Senior FPGA & Digital Hardware Engineer↗ GE HealthCareWaukesha, WI, US 2d Design and verify digital circuit boards and FPGA-based subsystems for high-performance MRI data acquisition, control, processing, and communications.
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PD engineer BroadcomBGR-Sofia-Garitage Park - Bldg 2, BG 2d Designs and develops integrated circuits, overseeing the full ASIC development lifecycle from architecture definition and logic design to verification, documentation, and process flow evaluation.
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Senior ASIC RTL Design Engineer, AI Hardware CerebrasRemote $200k–$200k2d Design and develop next-generation Cerebras Wafer Scale Engine (WSE) AI chips, focusing on high-performance, power-efficient, and scalable RTL solutions.
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Physical design CAD engineer MarvellYokneam, IL 2d Physical design and methodology for next-generation high-performance processor chips in leading-edge CMOS processes for server, 5G/6G, automotive, and networking applications.
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ASIC Engineering Technical Leader (onsite) CiscoSan Jose, California, US $172k–$172k2d Define, design, and verify high-performance ASIC and subsystems for Cisco networking platforms, ensuring power, performance, and area goals.
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2027 Intern - SoC Digital Engineer MotorolasolutionsPlantation, FL, US 2d Develop the digital portion of mixed signal ICs for hi-reliability public safety communications systems using CMOS technologies.
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Digital IC Design Engineering Intern SemtechCAN - Burlington, ON, CA $54k–$54k2d Design RTL blocks and verify digital subsystems for next-generation mixed-signal ICs in data communications and broadcast video product lines.
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Senior Design Automation Engineer
AmazonAustin, Texas, United States
$185k–$250k2d
Develop automation to enable physical design teams to execute Package and PCB products from floor planning through tape out and manufacturing release for next-generation machine learning and data center ASICs.
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Physical Design Engineer AlteraSan Jose, California, United States $105k–$105k2d Physical implementation of next-generation FPGA products, optimizing designs for timing, power, area, and manufacturability.
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ASIC Engineer I, Annapurna Labs, Early Career - 2027↗ Amazon Web ServicesAustin, TX, US $116k–$116k2d Design and implement RTL for digital logic blocks and develop verification environments for custom silicon products like Graviton, Trainium, and Inferentia.
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Senior FPGA & Digital Hardware Engineer GehcWaukesha, US 2d Design and verify digital circuit boards and FPGA-based subsystems for high-performance data acquisition, control, processing, and communications in next-generation MRI platforms.
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Staff Engineer, Timing Samsung Electronics3900 N Capital of Texas Hwy, Austin, TX, USA $151k–$151k2d Ensure timing integrity and signoff readiness for next-generation GPU IPs used in premium smartphones and high-performance computing devices.
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Physical Design Engineer, ML4PD TenstorrentAustin $100k–$100k2d Physical design of high-performance chips for industry-leading AI/ML architectures, spanning implementation from synthesis through tapeout.
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Expert FPGA / ASIC Numérique - Architecture ou Vérification - Industrie - Toulouse Sopra-SteriaToulouse, Occitanie, fr 2d Expert in FPGA/ASIC digital architecture or verification for critical embedded and industrial systems with real-time and safety constraints.
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Qubit Control Physical Design Engineer IntelUS, Oregon, Hillsboro $142k–$142k3d Deliver high-performance physical designs for advanced semiconductor technologies, optimizing power, performance, and area (PPA) from synthesis to sign-off.
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Digital IC Design Engineer - USB Products Texas InstrumentsDallas, TX, United States 3d Design next-generation USB 2.0 and eUSB2 hubs, hosts, and bridges for Enterprise AI and IoT applications.
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Lead Application Engineer CadenceSHANGHAI, CN 3d Provide technical support for digital IC design implementation, product demonstrations, and sales presentations.
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Hardware / Performance Architect↗ Epic Blockchain TechnologiesNorth York, ON, CA $120k–$120k3d Define micro-architecture and performance modeling for a large, regular compute-array inference ASIC, translating system-level intent into block specifications for RTL and compiler teams.
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Physical Design Engineer- Singapore↗ Picoheart (sg) Pte. Ltd.Outram, S00, SG 3d Own physical implementation of critical blocks/subsystems/SOCs from netlist to GDS, driving PPA optimization and signoff closure.
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Digital Design Engineer AnalogdevicesIndia, Hyderabad 3d Design and develop digital integrated circuits, executing the complete design flow from specification to implementation for industry-standard interfaces.
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Principal Chip Lead, Silicon Co-Design Group NVIDIAUS, CA, Santa Clara $232k–$232k3d Technical lead for high-consequence silicon programs, accountable for end-to-end technical integrity and guiding co-design feature integration across architecture, design, validation, and manufacturing.
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Senior Physical Design Engineer↗
GoogleMountain View, CA, US
$163k–$163k3d
Develop full-chip ASIC RTL-to-GDS physical implementation to optimize Power, Performance, and Area (PPA) for Google's direct-to-consumer products.
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Staff SoC Architect GraphcoreBristol 3d Define SoC architecture for next-generation AI acceleration platforms, specifying subsystems, interfaces, and interconnects to guide implementation and validation.
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Physical Design Intern AmbiqmicroincSingapore 3d Intern role supporting block-level physical implementation for ultra-low power System-on-Chip (SoC) designs in advanced process nodes.
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Silicon Digital IP / Subsystem Architect AsteralabsBengaluru 3d Define architecture and technical direction for complex semiconductor IPs and subsystems, owning the definition from requirements through implementation.
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