ASIC Physical Design
2,711 open positions
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Graduate Digital Design Engineer CevaRa'anana, Israel today Designing DSP cores and baseband hardware accelerators for next-generation 5G modem IP targeting User Equipment and base stations, including space and satellite infrastructure.
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Physical Design Engineer Advanced Micro Devices, IncShanghai, China today Physical design of deep sub-micron GPU chips including block level floor planning, place&route, and physical verification.
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Principal Timing Design Engineer Renesas-ElectronicsPhú Mỹ, Ho Chi Minh, vn 1d Lead timing design, test design, or design management for MCUs/MPUs targeting consumer, industrial, and IoT applications.
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FPGA-Entwickler medizinische Lasersysteme (all gender) AltenRemote 1d Designing and implementing FPGA components for a medical laser system within an existing device control platform.
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ASIC/FPGA Methodology Engineer Artech LLCUSA $324480k–$519168k1d Develop and maintain methodologies for ASIC/FPGA design, verification, and implementation, integrating workflows and tools to support RTL design development.
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Senior Physical Design Engineer NVIDIAIsrael, Tel Aviv 1d Design high-speed communication chips (Networking Silicon) focusing on power, area, and performance optimization.
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Sr. Physical Design Engineer QualcommSanta Clara, California, United States of America $135k–$202k1d Define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for high performance, high quality, low power products.
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Associate Vice President, Engineering – DCE Connectivity Hardware MarvellSanta Clara, CA, US $242k–$363k1d Lead a globally distributed engineering organization to deliver high-performance electrical and optical connectivity silicon (retimers, gearboxes, AEC, PCIe switches, Co-Packaged Optics) for AI clusters, cloud data centers, and carrier networks.
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Hardware Design Engineer CiscoMilpitas, California, US $138k1d Own the end-to-end design and delivery of medium-to-complex hardware features for networking and compute applications.
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SoC Logic Design Engineer IntelUS, California, Santa Clara $106k–$149k1d Design and implement logic for SoC blocks and subsystems using RTL coding, integrating IP blocks into full chip designs to meet power, performance, area, and timing goals.
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Digital Design Engineer Siemens-EdaNew Cairo, EGY, Egypt $18k2d Design and develop synthesizable models for FPGA vendor library cells and DSP decomposition models for arithmetic blocks to support static and formal functional verification flows.
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Sr/Staff Digital Design Engineer LightmatterBoston, MA $123k–$175k3d Develop RTL modules with DFT considerations for an ASIC in next-generation AI computing architecture.
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Physical Design and CAD Engineer AsteralabsSan Jose $160k–$200k3d Technical Lead developing next-generation connectivity ASICs for cloud and AI infrastructure, combining Physical Design CAD methodology development with hands-on place-and-route implementation.
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Staff Engineer - CPU Design, RTL Development Info Way Solutions LLCUSA $130k3d Design and optimize high-performance CPU and SoC blocks from microarchitecture through RTL and physical implementation.
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