Senior ASIC Timing Engineer
Core
Lead timing analysis and closure for NVIDIA GPUs, CPUs, LPUs, and SoCs at block, cluster, and full chip levels.
Role type
Senior ASIC Timing Engineer
Builds
High-performance GPUs, CPUs, LPUs, and System-on-Chips (SoCs)
Domain
Semiconductor / Hardware Design / Deep Sub-micron Process Nodes
Deliverable
production ML models | product features
Required skills
Static Timing Analysis (STA), timing constraints generation, ECO implementation, crosstalk and noise analysis, physical design optimization (synthesis, placement, routing), deep sub-micron process modeling
Preferred skills
GPU/CPULPU/SoC domain expertise, logic synthesis and equivalence checking, DFT timing closure, AMS design timing, flow development and automation
Technologies
Industry standard STA and timing convergence tools
Responsibilities
Drive timing analysis and closure processes; Collaborate with RTL, DFX, and Clock teams to devise timing closure strategies; Contribute to innovative projects by improving timing convergence flows
Seniority
Senior, hands-on IC
