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Hardware & Physical Engineering
› Analog IC Design
Analog IC Design
2,201 open positions
SR R&D/PRODUCT DVL ENGINEER
Jobgether
Remote
$115k–$145k
today
Drive electrical design, simulation, and validation of high-speed connectivity products for data centers and wireless infrastructure.
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Staff Engineer Mask Design
Infineon
Penang
today
Develop and verify custom IC layouts, floorplan blocks, and top-level routing for advanced semiconductor technologies.
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Hardware Engineer
Bosch-Group
València, VC, es
today
Define architecture of state-of-the-art integrated circuits (ICs) for radar and transceiver modules in the automotive sector, translating customer needs into concrete specifications for analog and digital design teams.
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PLL Design Engineer
Advanced Micro Devices, Inc
San Diego, California
today
Design complex building blocks of Phase Locked Loops (PLL) including architecture development and transistor-level circuit design for AMD processors.
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Circuit Design PhD Problem Author and AI Trainer
Mercor
Remote
$177k
1d
Create original, free-response engineering problems based on real industry scenarios and develop complete, expert-level solutions for them.
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PCB Signal & Power Integrity Engineer
Artech LLC
USA
$259584k–$389376k
1d
Develop code and scripts for Cadence tools to streamline PCB setup, support floor planning and routing constraints, and run high-priority simulations to resolve signal and power integrity challenges.
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Senior Director, Engineering
Jobgether
Canada
1d
Lead the architecture, development, and delivery of advanced embedded memory IP solutions for semiconductor applications, serving as a senior technical partner to customers.
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Hardware Engineer
↗
Bosch
Valencia, VC, ES
1d
Define architecture of state-of-the-art integrated circuits (ICs) for radar and transceiver modules in the automotive sector, translating customer needs into concrete specifications for analog and digital design teams.
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Staff Analog/Mixed-Signal IC Design Engineer
↗
Analog Devices
Valencia, VC, ES
1d
Design and develop high-performance precision analog/mixed-signal ICs (amplifiers, ADCs, DACs) for the Intelligent Edge, bridging physical and digital worlds.
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Staff Analog/Mixed-Signal IC Design Engineer
Analogdevices
Spain, Valencia, Cortes Valencianas
1d
Develop transistor-level designs for high-performance precision analog/mixed-signal ICs using fine-line CMOS and other process technologies.
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Head of hardware – CMOS Sensor Electronics
↗
Tmrw Silicon
Valencia, Valencian Community, Spain
1d
Lead hardware design for nanophotonics-enhanced CMOS sensor electronics, from characterization boards to application-specific devices.
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Analog Layout Engineer
Ciena
Remote-Mexico
1d
Develop physical layouts for analog and mixed-signal integrated circuits by translating schematic designs into manufacturable layouts.
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ASIC Engineering Analog Design Leader | high-speed optical transceiver circuits (modulator drivers, TIAs, CDRs, PLLs, ADC/DAC) | 10+ years
Cisco
Bangalore, India
1d
Lead full-chip electrical specifications and mixed-signal design for Cisco's next-generation silicon photonics driver integrated circuits supporting 100G/200G/400G per Lambda solutions.
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Senior Director, Engineering
↗
Silvaco
Remote, CA
2d
Lead architecture, design, and delivery of embedded memory compilers (SRAM, ROM, register files, RAM) for SoC integration, serving as the senior technical voice in customer engagements.
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Technical Project Lead - IC Design (d/m/f)
↗
ams OSRAM
Premstätten, Styria, Austria
2d
Leads R&D product development for an integrated circuit (IC) project, managing the design team and external providers to deliver analog/mixed-signal ICs.
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Senior Hardware Engineer, Analog & Mixed-Signal
Voyant Photonics
USA
$140k–$170k
3d
Define analog and mixed-signal architecture for next-generation LiDAR modules, serving robotics, autonomous vehicles, and industrial automation.
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MTS Silicon Design Engineer
Advanced Micro Devices, Inc
San Jose, California
3d
Research, design, develop, and test electronic components and systems for semiconductor manufacturing, overseeing ASIC development from architecture to layout and verification.
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MTS Silicon Design Engineer
Advanced Micro Devices, Inc
San Jose, California
3d
Research, design, develop, and test electronic components and systems for semiconductor manufacturing, focusing on custom mixed-signal design development and complex integrated circuit layout.
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MTS Mask Design Engineer
Advanced Micro Devices, Inc
Remote
3d
Research, design, develop, and test electronic components and systems for semiconductor and related device manufacturing, specifically verifying mask designs against leading edge physical and electrical checks.
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SMTS Silicon Design Engineer
Advanced Micro Devices, Inc
San Diego, California
3d
Research, design, develop, and test electronic components and systems for semiconductor manufacturing, focusing on ASIC development and complex integrated circuit layout.
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High Speed DAC Design Expert
Advanced Micro Devices, Inc
San Jose, California
3d
Designing high-performance analog/mixed-signal circuit blocks for Serdes transceivers, including high-speed DACs/ADCs, clocking, and analog front-end circuits.
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Sr. Systems Design Engineer
Advanced Micro Devices, Inc
Santa Clara, California
3d
Develop chip package board Power Delivery Network (PDN) models and perform simulations to verify supply noise, impedance, and transient response.
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Mixed Signal Custom Layout - Temporary/Seasonal
Advanced Micro Devices, Inc
MARKHAM, Canada
3d
Design transistor-level layouts for digital and analog circuits (PLL, DLL, VCO, DAC, etc.) using Cadence Virtuoso and industry-leading foundry technology.
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2027 Analog & Mixed-Signal Design Intern
Advanced Micro Devices, Inc
Cork, Ireland
4d
Design high-speed analog and mixed-signal integrated circuits, specifically SerDes solutions, for AMD CPU, GPU, and FPGA products.
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Staff PDK Engineer
Renesas-Electronics
Bengaluru, KA, in
4d
Develop, review, update, and release foundry Process Design Kits (PDKs) and design methodologies for various business units, providing CAD support and troubleshooting for circuit design and layout teams.
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Physical Design and Verification Engineer
Neuralink
Fremont - Campus
$131k–$265k
4d
Senior Physical Design Engineer owning block-to-full-chip implementation and multi-physics verification (thermal, mechanical, IR/EM) for advanced-node 3DIC products.
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Associate Designer, PCB Layout Engineering
Analogdevices
India, Bangalore, RMZ
4d
Design and layout of printed circuit boards (PCBs) for analog and mixed-signal semiconductor solutions.
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全光连接光学集成工程师
Huawei
Wuhan, China
4d
Design and develop optical engine processes for Optical Circuit Switches (OCS), including chip, optical component, and supporting component process design to achieve key performance targets like insertion loss.
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FY27 Intern - PMU Internship - 6 months, Cambridge
Qualcomm
Cambridge, United Kingdom
4d
Summer placement to develop system-level solutions and architecture for reducing deep sleep current and/or external component count in analog blocks for future products.
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Heterogeneous Integration Physical Design Engineer
Qualcomm
Hsinchu City, Taiwan
4d
Define, model, design, optimize, verify, validate, and document IP (block/SoC) development for high-performance, low-power products, with a focus on 2.5D/3D heterogeneous integration and System-Technology Co-Optimization (STCO).
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Senior Mask Design Engineer - Hardware
NVIDIA
Canada, Toronto
4d
Performing physical layout for high-speed mixed-signal circuits (PLLs, SerDes, ADCs, ESD) in sub-micron CMOS technologies.
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Distinguished Signal and Power Integrity Engineer
NVIDIA
US, CA, Santa Clara
$320k
4d
Lead corporate-level strategies and technical direction for high-speed signaling technologies across advanced semiconductor packaging, sockets, and connectors for next-gen AI and HPC platforms.
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Sr. Engineer, System Level Test
Qualcomm
San Diego, California, United States of America
4d
Plan, design, optimize, verify, and test electronic systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and DSP systems to bring-up yield and launch cutting-edge products.
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Principal Analog Design Engineer (Data-Converters)
Nxp
Noida, IN
4d
Lead the end-to-end design, verification, and silicon validation of high-performance Analog Mixed-Signal IPs, specifically Data Converters (ADC/DAC), serving product teams and SoC integration.
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Silicon Photonics - Reference Design Engineer
GlobalFoundries
IND - Karnataka - Bengaluru - North, IN
4d
Design silicon photonics circuits (PICs) for pluggables, NPO, and CPO applications to meet target specifications and accelerate customer time-to-design.
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Postdoctoral Researcher - High Step-down Power Converter Topologies, 1 FTE, School of Engineering, 012016
↗
University of Galway
Galway, County Galway, Ireland
€47k–€60k
4d
Developing high step-down power converter topologies for AI computing using optimal 3D transformers-on-silicon and advanced heterogeneous integration packaging.
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Research Assistant (Integrated circuit design)
Ntu
NTU Main Campus, Singapore
4d
Junior hardware research engineer deriving new electronic circuit designs, building verification hardware, and performing IC layout and measurements for research grants.
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ENGINEER NCG - HBM LAYOUT
↗
Micron Technology
Tlaquepaque, JAL, MX
4d
IC layout design for leaf cells, standard cells, and sub-blocks within memory and storage solutions.
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PCB HW Design Engineer
Broadcom
USA-Allentown-1110 American Parkway NE
$122k
4d
Design and develop Bench and System Level Test (SLT) PCBs for Broadcom integrated circuit products targeting hyperscale data center and AI applications.
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Research Assistant (Integrated circuit design)
↗
Nanyang Technological University
Nanyang Avenue, S00, SG
4d
Junior hardware research engineer assisting a research group in deriving new electronic circuit designs, building verification hardware, and performing simulations for integrated circuit design projects.
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ASIC Packaging SI/PI Engineer (Hybrid)
Cisco
San Jose, California, US
$126k
4d
Develop, document, and implement design rules for ultra-high-speed signaling and analyze substrate signal and power integrity (SI/PI) for next-generation ASIC packaging.
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Signal and Power Integrity Technical Leader | 8 to 15 years | Bangalore
Cisco
Bangalore, India
4d
Lead signal and power integrity (SI/PI) design and analysis for high-speed interconnects, ASICs, packages, and PCBs in next-gen networking and AI/ML products.
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Distinguished Signal and Power Integrity Engineer
NVIDIA
US, CA, Santa Clara
$320k
4d
Lead corporate-level strategies and technical direction for high-speed signaling, interconnect, and advanced semiconductor packaging solutions for next-gen AI, HPC, and ultra-mobile platforms.
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Analog IC Design Engineer | Remote
↗
Singapore Advanced Thin Film Materials Private Limited
Remote
4d
Design and develop high-performance analog-to-digital mixed-signal chip R&D, focusing on signal chain systems (AFE/ADC) and power management modules (LDO/BG/POR).
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Foundry Interface Engineer – PMIC / Analog
Apple
Cupertino, United States of America
4d
Foundry Interface Engineer for PMIC/Analog products, bridging design teams and semiconductor foundries to enable process technology and product development.
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Advanced Packaging Development Engineer
Apple
San Francisco Bay Area, United States of America
4d
Lead the definition, development, and qualification of next-generation 2.5D and 3D packaging technologies for future products.
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Baseband Hardware Design Engineer
Apple
Sunnyvale, United States of America
4d
Designing the architecture, schematics, layout, and integration of the digital and power management domain for Apple's wireless chipsets.
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Staff Signal Integrity Engineer - Product Development and R&D
↗
TE Connectivity
Hermosillo, SON, MX
4d
Electrical design, simulation, and verification of high-speed products in connectors and cable assemblies for datacenter and wireless infrastructure.
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ENGINEER NCG - HBM LAYOUT
Micron
Tlaquepaque, Jalisco, Mexico
4d
IC layout design for leaf cells, standard cells, and sub-blocks in memory and storage solutions.
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DMTS, DRAM Systems
Micron
San Jose, California, United States of America
$216k–$430k
4d
Lead architecture analysis for AI, cloud, and enterprise platforms, connecting DRAM device behavior to system-level performance and roadmap decisions.
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