Physical Design Implementation and STA Lead
Core
Lead physical design implementation and static timing analysis (STA) for next-generation FPGA SoCs, driving closure from floorplanning to signoff.
Role type
Senior IC physical design implementation and STA lead
Builds
High-performance FPGA System-on-Chip (SoC) blocks and subsystems
Domain
Semiconductor / FPGA / Physical Design
Required skills
Physical design implementation, Static Timing Analysis (STA), Synopsys PrimeTime, Tcl, Python, Floorplanning, Place-and-route, Clock tree synthesis (CTS), ECO closure, Signoff (DRC/LVS/IR drop), Multi-mode multi-corner (MMMC) analysis
Preferred skills
Advanced process nodes (7nm/5nm), SoC top-level timing closure, High-speed interfaces (PCIe, SerDes, DDR, HBM), Master's degree
Technologies
Synopsys PrimeTime, Tcl, Python, FPGA tools
Responsibilities
Lead block-level physical implementation including synthesis, floorplanning, place-and-route, CTS, and optimization; Perform static timing analysis across PVT corners to resolve setup/hold violations; Execute signoff activities including IR drop, electromigration, DRC, and LVS; Develop automation scripts to streamline workflows; Mentor junior engineers on implementation methodologies.
Seniority
Senior, hands-on IC with project leadership
