Physical Design Implementation and STA Lead
Core
Lead physical design implementation and static timing analysis (STA) for next-generation FPGA SoCs, driving closure from floorplanning through signoff.
Role type
Senior IC physical design implementation and STA lead
Builds
High-performance FPGA System-on-Chip (SoC) blocks and subsystems
Domain
Semiconductor / FPGA / Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
block-level physical implementation, static timing analysis (STA), Synopsys PrimeTime, Tcl/Python automation, multi-mode multi-corner (MMMC) analysis, clock tree synthesis (CTS), place-and-route, ECO closure, IR drop analysis, DRC/LVS verification
Preferred skills
advanced process nodes (7nm/5nm), SoC top-level timing closure, high-speed interface implementation (PCIe, SerDes, DDR, HBM), Master's degree in EE/CE
Technologies
Synopsys PrimeTime, Tcl, Python, SDC, UPF
Responsibilities
Lead block-level physical implementation including synthesis, floorplanning, place-and-route, CTS, and optimization; Perform STA and resolve timing violations across PVT corners; Execute signoff activities including IR drop, EM, DRC, and LVS; Develop automation scripts to streamline workflows; Mentor junior engineers on implementation methodologies.
Seniority
Senior, hands-on IC with project leadership
