Design Engineer II
Core
Developing, automating, and maintaining EDA flows and scripts for physical implementation of IP cores and soft controllers to optimize performance and power.
Role type
Senior IC physical design engineer (ASIC backend)
Builds
Production-ready ASIC IP cores and soft controllers optimized for performance and power on advanced process nodes.
Domain
Semiconductor EDA / ASIC Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Physical design experience in ASIC design environment, Complete ASIC Design Flow knowledge (Synthesis, Physical Designing, Timing Analysis, Power Analysis, Formal Verification), Logic Synthesis and PPA optimization techniques, Logic Equivalence Checks (LEC) debug experience, Synthesis flow development and debugging, Scripting (Python, Tcl), EDA tools (Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus, Fusion Compiler)
Preferred skills
Experience with AI tools for design automation, Experience with TSMC, Intel, Samsung, and Rapidus foundries
Technologies
Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus, Fusion Compiler, Python, Tcl, TSMC, Intel, Samsung, Rapidus
Responsibilities
Develop automation scripts using AI tools to reduce design execution turnaround time, Manage regression infrastructure that tracks quality of RTL/flow development and PPA of key designs, Perform PPA characterization and optimization of flow for performance-oriented and power-oriented best-in-class IP cores
Seniority
Mid-level, hands-on IC