Principal NoC IP Micro-Architect
Core
Designing and leading the end-to-end architecture, microarchitecture, and RTL development of scalable Network-on-Chip (NoC) IP solutions for next-generation FPGA platforms.
Role type
Principal NoC IP Micro-Architect
Builds
High-performance interconnect solutions for Altera's FPGA platforms
Domain
Semiconductor / FPGA / SoC Interconnect
Deliverable
production ML models | product features
Required skills
SoC interconnect architecture, NoC fabrics, RTL design, System Verilog, VCS/Synopsys simulators, C/C++/Perl/Python/TCL/Unix Shell scripting, FPGA design, RTL validation, EDA tools (timing constraints, lint, CDC, RDC, DFT), AI/automation in development
Preferred skills
FPGA design and programming, RTL validation, AI usage in development process
Technologies
System Verilog, VCS, Synopsys, C, C++, Perl, Python, TCL, Unix Shell, EDA tools
Responsibilities
Develop logic design, RTL coding, and simulation for NoC IPs; define architecture and microarchitecture features; create prototypes and specify system requirements; design logic diagrams and codes for implementation; deliver software models for device bring-up; apply RTL implementation techniques for PPA optimization; review verification plans and resolve failing tests; mentor technical members and guide the NoC team
Seniority
Principal, hands-on IC with technical leadership
