Principal Hardware ASIC Architect engineer
Core
Define and own architecture for compute, memory, interconnect, and high-speed interface subsystems in AI inference chips, balancing performance, power, and area (PPA) from concept through silicon.
Role type
Principal Hardware ASIC Architect (AI Inference Accelerators)
Builds
Next-generation AI inference accelerators
Domain
Semiconductor / AI Hardware
Deliverable
production ML models
Required skills
SOC architecture, Micro-architecture design, RTL coding, System-level performance/power analysis, PPA optimization, Hardware-Software co-design, AI inference workload modeling, Verilog/SystemVerilog, C/C++, Python/Tcl/Perl scripting
Preferred skills
AI accelerators experience, DSPs, high-performance CPUs/GPUs, Performance modeling frameworks, EDA tools, Power/performance analysis
Technologies
Verilog, SystemVerilog, Python, Tcl, Perl, C, C++
Responsibilities
Define product features and capabilities for compute, memory, and interconnect subsystems; Collaborate with software teams to co-optimize hardware for AI workloads; Review and guide RTL implementation for consistency with architectural intent; Lead PPA analysis and trade-off discussions; Develop and maintain high-level architecture and performance models; Validate model predictions against RTL or emulation results
Seniority
Principal, hands-on IC