Staff Digital Design Engineer
Core
Architecting, designing, and integrating low-power digital circuits for mixed-signal data conversion and power management products in advanced process nodes.
Role type
Staff Digital Design Engineer (ASIC/SoC)
Builds
Mixed-signal data conversion and power management silicon solutions
Domain
Semiconductor / Embedded Systems / Power Management
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Digital RTL design (Verilog/SystemVerilog), ASIC design methodology, Timing analysis and closure, Low-power design techniques, Block-level & chip-level verification, Debugging RTL and gate-level simulations, Mixed-signal design flow, P&R interaction, DFT strategy, Test-bench development
Preferred skills
Digital Signal Processing (DSP) concepts, Flow automation scripting, Advanced verification methodologies (UVM), Industry-standard protocols (AMBA, I2C), Power analysis and optimization
Technologies
Verilog, SystemVerilog, UVM, AMBA, I2C, UPF, Lint, CDC, RDC, STA
Responsibilities
Architect low-power digital circuits for mixed-signal applications, Design digital RTL meeting timing/area/power specs, Integrate designs and run block/top-level simulations, Mentor junior engineers and lead technical reviews, Collaborate with analog and verification teams on test scenarios, Develop design documents and support silicon evaluation
Seniority
Staff, technical leadership & mentorship
