Staff Engineer, Physical Design
Core
Lead MCU/subsystem/block-level physical design closure efforts for complex hierarchical SoCs, focusing on timing, congestion, power integrity, and implementation.
Role type
Staff Engineer, Physical Design (Subsystem/Block Level)
Builds
Subsystem-level physical implementations and closure flows for embedded SoCs
Domain
Semiconductor / VLSI Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
timing closure, congestion management, physical implementation, UPF (power domain implementation), clock domain integration, SoC floorplanning concepts, automation scripting (Tcl/Python/Perl), cross-functional collaboration, mentorship
Preferred skills
advanced node design experience (7nm/5nm), low-power design techniques, signoff platform expertise
Technologies
Synopsys ICC2, Cadence Innovus, PrimeTime, UPF
Responsibilities
Lead MCU/subsystem/block-level closure efforts, Collaborate with SoC-level teams on clocking and floor planning, Implement UPF for different power domains, Develop and refine subsystem closure methodologies and automation flows, Mentor physical design engineers, Work cross-functionally with RTL, STA, power, verification, and backend teams, Proactively identify and mitigate physical design risks
Seniority
Staff, hands-on IC with mentorship responsibilities