Senior STA Engineer
Core
Senior STA Engineer responsible for timing sign-off, constraint development, and margin methodology for mobile CPU blocks in next-generation SoCs.
Role type
Senior IC STA Engineer (CPU blocks)
Builds
Mobile SoCs for smartphones, AI PCs, and automotive applications
Domain
Semiconductor design, mobile CPUs, 5G/6G, AI
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
STA sign-off, constraint development, multi-scenario regression, ECO generation, AOCV/POCV margining, clock tree analysis, SDC creation, Tempus/PrimeTime usage
Preferred skills
Advanced margining methodologies, SoC integration, worldwide forum participation
Technologies
Tempus, PrimeTime, ETM, Hyperscale
Responsibilities
Own block-level STA sign-off including constraint development and timing closure; Generate and drive timing and power ECOs; Partner with RTL and DFT teams to define functional and test-mode constraints; Develop and champion advanced margining methodologies (AOCV/POCV); Analyze clock tree quality and guide physical implementation; Build custom sign-off recipes for power recovery and timing closure; Deliver timing models and SDC/timing budgets for SoC integration
Seniority
Senior, hands-on IC
