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Senior ASIC Design Engineer

US, CA, Santa Clara💼 Full-time💰 $168,000–$168,000🗓 2026-07-15 → 2026-09-26

Core

Implement, document, and deliver high-performance, area, and power-efficient RTL for NVIDIA's leading SoCs and GPUs, focusing on micro-architecture, scheduling, and interconnects.

Role type

Senior IC ASIC Design Engineer (GPU/SoC)

Builds

High-performance GPU and SoC silicon for consumer graphics, self-driving cars, and AI platforms.

Domain

Semiconductor / VLSI / Computer Architecture

Deliverable

production ML models | product features

Required skills

RTL development (Verilog), micro-architecture design, ASIC design flow (synthesis, timing analysis), digital systems, VLSI design, computer architecture, computer arithmetic, arbiters, scheduling, synchronization, bus protocols, interconnect networks, caches

Preferred skills

C/C++, Python, Perl, silicon debugging, post-silicon validation

Technologies

Verilog, GPU, SoC, RTL, Synthesis, Timing Analysis

Responsibilities

Implement and document RTL to achieve design targets; Analyze architectural trade-offs based on performance and system limitations; Craft micro-architecture and deliver verified, synthesis/timing clean designs; Collaborate with architects, verification, and back-end teams; Work on IPs like work schedulers, interrupt controllers, and DMA engines; Architect features to support silicon debug and post-silicon validation.

Seniority

Senior, hands-on IC

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