Physical Design Engineer - STA
Core
Drive static timing analysis (STA) and closure for complex, high-performance RISC-V CPUs and AI SoCs to meet aggressive performance goals.
Role type
Senior IC physical design engineer (STA)
Builds
High-performance RISC-V CPUs and AI System-on-Chips (SoCs)
Domain
Semiconductor / AI Hardware
Deliverable
production ML models
Required skills
Static timing analysis (STA), SDC constraint creation, ECO generation, Python scripting, Perl scripting, TCL scripting, SPICE modeling, worst-case corner analysis, noise and crosstalk analysis
Preferred skills
Experience with sub-micron process technologies, automation flow development
Technologies
Python, Perl, TCL, SPICE
Responsibilities
Debug timing constraints, optimize timing paths, ensure chip performance targets across corners and modes, develop scripts to improve timing closure workflows
Seniority
Senior, hands-on IC
