Associate Staff/Staff Implementation Design Engineer
Core
Leading and hands-on execution of backend (BE) implementation flow for high-performance SoCs and ASICs, ensuring timing closure and PPA optimization.
Role type
Associate Staff/Staff Implementation Design Engineer
Builds
High-performance System-on-Chips (SoCs) and Application-Specific Integrated Circuits (ASICs)
Domain
Semiconductor / VLSI Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Backend implementation flow (Synthesis, Place & Route, STA, LEC, CTS), Timing sign-off, Low-power methodologies (UPF, power gating), EDA tool expertise (Cadence, Synopsys), Constraint development, PPA optimization
Preferred skills
Chip-level integration, DFT, Floor planning, Multi-clock/multi-voltage designs, Team leadership (4-10 members), Scripting automation (Perl/Tcl/Python)
Technologies
Cadence Genus, Innovus, Tempus, LEC, CLP; Synopsys ICC2, Fusion Compiler, PrimeTime
Responsibilities
Develop and manage timing constraints for RTL-to-GDSII flow; Execute Static Timing Analysis (STA) for digital blocks; Generate CTS specifications; Run Logical Equivalence checks; Develop low-power and UPF checks; Implement timing ECOs; Lead end-to-end physical design flow; Optimize PPA metrics; Mentor junior engineers
Seniority
Senior, hands-on IC with team leadership