Senior RTL Design Engineer
Core
Designing sophisticated micro-architecture and RTL for innovative IPs used in Physical AI, Automotive, Edge, and Infrastructure computing.
Role type
Senior RTL Design Engineer
Builds
Digital IPs for AI, automotive, and edge computing products
Domain
Semiconductor hardware design (ASIC/FPGA)
Deliverable
production ML models
Required skills
System Verilog, Verilog, VHDL, ASIC design methodology, timing analysis, power management, static design checks, synthesis, IP signoff
Preferred skills
AMBA ACE-Lite/AXI protocols, PCIe, I/O virtualization, SystemVerilog Assertions (SVA), formal verification, scripting (Perl/Tcl/Python/C shell), Functional Safety
Technologies
System Verilog, Verilog, VHDL, Perl, Tcl, C shell, Python
Responsibilities
Analyze specifications to understand implementation challenges, plan and coordinate tasks, collaborate with verification and implementation teams to meet functional/power/performance requirements, improve design methodology
Seniority
Senior, hands-on IC
