Firmware Design Engineer
Core
Developing physical IP for industry-standard high-speed serial-link protocols, specifically firmware for SERDES PHYs.
Role type
Firmware Design Engineer (High-Speed SERDES PHY)
Builds
Physical IP blocks for system-on-chip (SoC) designs
Domain
Semiconductor / Electronic Design Automation (EDA) / High-Speed Serial Communication
Deliverable
production ML models | product features | infrastructure
Required skills
C/C++ programming, Python programming, digital verification (UVM, SystemVerilog), wireline communication principles, mixed-signal circuit design, digital signal processing
Preferred skills
None explicitly stated as preferred
Technologies
C, C++, Python, UVM, SystemVerilog
Responsibilities
Develop firmware architecture and implement defined features for high-speed SERDES; Debug and fix firmware issues found in verification simulations; Support post-silicon testing and validation to identify and resolve firmware/hardware functionality and performance issues; Collaborate with product engineering and system validation teams to debug IP issues in the field and provide hot fixes; Build system-level prototype control software to develop and validate adaptation, equalization, and control algorithms.
Seniority
Mid-level to Senior, hands-on IC