Sr. Staff Physical Design Timing Engineer (STA)
Core
Drive backend digital execution and timing closure for leading-edge silicon photonics chips in extreme-scale data centers.
Role type
Sr. Staff Physical Design Timing Engineer (STA)
Builds
3D-stacked photonics engines (Passage™) connecting thousands to millions of processors for AI and HPC workloads.
Domain
Semiconductor hardware design / Silicon photonics / Data center infrastructure
Deliverable
production ML models
Required skills
STA sign-off, timing constraints development, timing closure, synthesis, place and route, clock tree building, on-chip variation derates, multi-mode multi-corner constraints, TCL/Python/Perl/Shell scripting, power/performance/area tradeoff analysis
Preferred skills
Master's degree in EE/CE, 8+ years hands-on ASIC STA experience
Technologies
Cadence, Synopsys, Tempime, PrimeTime
Responsibilities
Drive STA sign-off for flagship silicon photonics chips; analyze fab guidelines and incorporate sign-off corners/margins/derates; collaborate with architecture/RTL/DFT teams to develop timing modes and constraints; analyze power/performance/area tradeoffs; run full-chip STA and project timing summaries; automate timing ECO generation; document best practices.
Seniority
Sr. Staff, hands-on IC
