Top Level Physical Design Engineer
Core
Senior-level Physical Design Engineer driving top-level implementation of complex AI and CPU System-on-Chip designs, orchestrating cross-disciplinary collaboration for floorplans, power grids, and clock networks.
Role type
Senior IC Physical Design Engineer (Full-Chip SOC)
Builds
High-performance AI accelerators and RISC-V CPUs at the System-on-Chip level
Domain
Semiconductor / AI Hardware / Chip Design
Deliverable
production ML models
Required skills
hierarchical floorplanning, fabric implementation, power grid design, global clock distribution, bump planning, RDL implementation, multi-voltage domain design, timing closure, EM/IR analysis, physical verification
Preferred skills
chiplet integration, next-generation packaging co-design
Technologies
RISC-V, SOC, multi-voltage domains
Responsibilities
Implement sophisticated floorplans, power grids, and clock networks; manage complexity of full-chip physical design; drive design closure while meeting aggressive schedules; collaborate with architecture, RTL, and packaging teams.
Seniority
Senior, hands-on IC
