Senior DFT Engineer, Architecture
Core
Design and integrate multiple chiplets into a System-in-package and implement DFT for high-speed CPU core design.
Role type
Senior DFT Engineer (Architecture)
Builds
High-performance RISC-V CPU chips and System-in-package solutions
Domain
Semiconductor / AI Hardware / Digital Design
Deliverable
production ML models | product features | infrastructure
Required skills
DFT implementation, scan chain insertion, memory BIST, JTAG, ATPG analysis, EDA scripting (TCL/Python), formal verification, silicon bring-up/debug, cross-functional collaboration
Preferred skills
Japanese fluency, Japanese work visa eligibility
Technologies
Cadence, Synopsys, Siemens, RISC-V
Responsibilities
Build chip-level DFT strategies, insert DFTs (scan chains, memory BIST, JTAG), collaborate with RTL/physical design/verification teams, script and automate DFT flows, run and analyze ATPG reports, support silicon bring-up and debug
Seniority
Senior, hands-on IC
