Principal SoC Circuit Architect
Core
Define high-speed IO PHYs (Ethernet, HBM4/4E/5), signal/power integrity, and end-to-end power delivery solutions for SoCs.
Role type
Principal SoC Circuit Architect
Builds
SoC level reference clocking, digital clocking methodology, and power delivery solutions.
Domain
Semiconductor / High-speed digital design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SoC level circuit architecture and design, PLL and clocking solutions for AI SoCs, High Speed IO PHY design, Signal Integrity, Package/substrate design, PCB design for power delivery
Preferred skills
Experience with HBM4/4E/5, D2D participation
Technologies
Ethernet, HBM4/4E/5, PLL, SoC
Responsibilities
Define high-speed IO PHYs, supervise signal and power integrity, define end-to-end power delivery solutions, define REFCLK and digital clocking methodology, partner with package and System design teams, participate in SoC level memory definition
Seniority
Principal, hands-on IC
