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Principal SoC Circuit Architect

United States, California, Mountain View💼 Full-time🗓 2026-07-14 → 2026-07-31

Core

Define high-speed IO PHYs (Ethernet, HBM4/4E/5), signal/power integrity, and end-to-end power delivery solutions for SoCs.

Role type

Principal SoC Circuit Architect

Builds

SoC level reference clocking, digital clocking methodology, and power delivery solutions.

Domain

Semiconductor / High-speed digital design

Deliverable

production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work

Required skills

SoC level circuit architecture and design, PLL and clocking solutions for AI SoCs, High Speed IO PHY design, Signal Integrity, Package/substrate design, PCB design for power delivery

Preferred skills

Experience with HBM4/4E/5, D2D participation

Technologies

Ethernet, HBM4/4E/5, PLL, SoC

Responsibilities

Define high-speed IO PHYs, supervise signal and power integrity, define end-to-end power delivery solutions, define REFCLK and digital clocking methodology, partner with package and System design teams, participate in SoC level memory definition

Seniority

Principal, hands-on IC

Rewrite
## About the role - Soc level definition of High-speed IO PHYs like Ethernet, HBM4/4E/5, D2D - Participation and quality supervision of Signal and Power Integrity - Define and quality control of end-to-end Power delivery solutions - Soc level REFCLK and digital clocking definition and clock methodology and quality simulations - Participating in SoC technology definitions partnering with package and System design teams - Participate in SoC level Memory definition and partner with custom memory development team in defining new memory related IPs ## Requirements - Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience - OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience - OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience - OR equivalent experience. - 15+ years of experience in Soc level Circuit architecture and design with MSEE - OR 12+ years of experience in the same with PhD in Electrical Engineering - Experience in PLL and Clocking solutions of AI SoC's - Experience in High Speed IO PHY design and Signal Integrity - Familiarity with Package/substrate design issues on signals and Power delivery - Familiarity with PCB design especially related to power delivery of AI SoC's ## What we offer - This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. - As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. - To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. - Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
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