Chiplet Design Architect
Core
Define architecture for next-generation chiplet-based compute platforms enabling high-performance RISC-V CPUs within scalable System-in-Package (SiP) solutions.
Role type
Senior IC CPU Chiplet Architect
Builds
Scalable System-in-Package (SiP) solutions with high-performance RISC-V CPUs
Domain
Semiconductor / High-performance computing / AI platforms
Deliverable
production ML models
Required skills
SoC or chiplet architecture, PCI Express Root Complex (RCiEP), coherent fabrics (CHI-C2C), IOMMU, ATS/PRI, MSI, CXL.mem, confidential computing (TEE-I/O), system management (boot, reset, debug, power management), cross-functional architecture leadership
Preferred skills
RISC-V platform development, third-party IP integration, hardware/firmware/system software mastery
Technologies
RISC-V, PCIe, CXL, TEE-I/O, CHI-C2C
Responsibilities
Define architecture for next-generation chiplet-based compute platforms, own key platform subsystems including PCIe and die-to-die connectivity, work closely with architecture, hardware, software, and external IP partners to deliver robust chiplet architectures
Seniority
Senior, hands-on IC
