Staff Engineer, Physical Design
Core
Implement high-performance blocks for industry-leading CPU and AI/ML architectures, owning the complete implementation flow from synthesis to tapeout.
Role type
Staff Physical Design Engineer (SOC/ASIC)
Builds
High-performance RISC-V CPUs and AI/ML accelerators on advanced process nodes
Domain
Semiconductor / Hardware Design / AI Infrastructure
Deliverable
production ML models | product features
Required skills
SOC/ASIC physical design, synthesis, PnR, timing closure, PPA optimization, RTL collaboration, debugging complex design hierarchies, advanced node challenges, low-power design techniques (power gating, multi-Vt, voltage scaling), flow development to signoff
Preferred skills
Experience with chiplet architectures, early architecture physical design requirements
Technologies
Innovus, PrimeTime, RedHawk, Tcl, Perl, Python
Responsibilities
Own complete implementation flow from synthesis to tapeout, optimize PPA through innovative implementation techniques, debug complex issues across design hierarchies, drive physical design requirements from early architecture through final signoff
Seniority
Staff, hands-on IC