ASIC Physical Design
1,421 open positions
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DSP Firmware Engineer MarvellCordoba, Argentina 6mo Design, simulate, implement, and validate DSP ASICs for coherent optical transmission in fiber networks.
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Physical Design Engineer MediaTekBangalore 6mo Own planning, execution, and closure of complex digital blocks, managing floorplanning, placement, CTS, routing, and timing closure to ensure signoff readiness.
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Digital Design Manager Texas InstrumentsBengaluru, Karnataka, India 6mo End-to-end delivery of the first T28 industrial ASIC, combining full chip ownership with RTL team leadership to ensure first-time-right silicon and scalable architecture.
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Design Engineer BroadcomUSA-Colorado-Fort Collins-4380 Ziegler Road $60k–$60k7mo Physical implementation of high-performance custom CMOS ASICs for AI, Cellular, Networking, Computing, and Storage products.
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Firmware Development Engineer AlteraJerusalem, Israel 7mo Develop firmware for multi-protocol high-speed SERDES (up to 256Gbps) governing DSP and analog blocks, ensuring seamless interface management with higher-level system layers.
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Senior Physical Design Engineer Enchargeai36India 7mo Lead physical implementation of complex silicon blocks from synthesis to sign-off, optimizing Power, Performance, and Area (PPA) for edge-to-cloud AI hardware.
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Electrical Engineer CerebrasHeadquarters/Sunnyvale Office $150k–$150k7mo Lead printed circuit board design and electrical specification for Cerebras' world's largest AI chip, enabling ultra-high-speed AI training and inference.
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Sr Principal Design Engineer CadencePUNE 04, IN 7mo Owns full DFT lifecycle for high-speed, low-power chip designs, defining test architecture and implementing RTL changes to ensure testability and timing closure.
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STA Synthesis Engineer Samsung ElectronicsSSIR, Goldstone, Bangalore, India 7mo Own timing constraints and drive timing closure for image sensor full chip and sub-system levels, including pre/post-layout analysis and ECO generation.
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Application Engineer- Prototyping Siemens-EdaBangalore, IND, India 7mo Deploy FPGA prototyping software and hardware solutions at customer sites, guide design bring-up, and collaborate with R&D to solve problems and improve product methodology.
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Staff Digital Design Engineer ON SemiconductorBangalore, Karnataka, India 7mo Lead digital design architecture, RTL, low power design, synthesis, and timing analysis for power management chips including DC-DC PMIC, multiphase controllers, and LED drivers.
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Director - Silicon Logical Design AxeleraRemote 7mo Lead and scale the digital design organization to architect, implement, and integrate complex AI accelerator SoCs from specification through tape-out.
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Senior ASIC Design Engineer NxpPune 8mo Designing wireless MAC controllers and system-level development for next-generation IoT connectivity chips.
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Staff Physical Design Engineer AnalogdevicesCLOSED-India, Bangalore, Aveda Meta 8mo Own end-to-end physical implementation (floorplanning, power planning, placement, CTS, routing, ECO) for complex blocks or subsystems across advanced technology nodes (e.g., 22nm, 16nm, 7nm, 5nm, 4nm) and lead a small group of engineers to achieve…
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Senior Physical Design Engineer NVIDIAIsrael, Yokneam 8mo Design high-speed communication chips by performing physical design of blocks under constraints to optimize power, area, and performance.
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Senior Physical Design Engineer - Signoff Methodology CiscoArmenia 8mo Develop and refine backend methodologies and flows from RTL to GDS, focusing on signoff disciplines for high-quality VLSI designs.
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Digital Design Engineer (New Grad) MonolithicpowerTaipei - Taiwan 8mo Design, development, and verification of digital and mixed-signal integrated circuits (ICs) for power management and portable/non-portable markets.
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Staff Design Engineer - Video ArmMultiple locations 9mo Design and test hardware modules for Image Signal Processors (ISPs), Display Processors, and Video codecs within Arm Compute Subsystems.
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Principal Engineer, STA & Synthesis Renesas-ElectronicsHyderabad, in 9mo Own synthesis and timing closure sign-off for low-power, chiplet-based MCU designs on cost-optimized mature process nodes.
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IC Design Engineer SilabsSingapore 9mo Designing digital blocks and integrating them into highly integrated mixed-signal SoCs for low-power MCU and Wireless products.
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