Physical Design Engineer
Core
Execute block-level physical design implementation for complex SoC/IP blocks in advanced technology nodes, ensuring PPA and reliability standards.
Role type
Senior IC physical design engineer
Builds
ASIC SoC blocks and IP cores
Domain
Semiconductor / VLSI / ASIC
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
floorplanning, placement and optimization, clock tree synthesis, routing, static timing analysis, DRC/LVS signoff, IR drop analysis, electromigration analysis, Tcl scripting, Python scripting, low-power design flows, multi-voltage design
Preferred skills
advanced node experience (16nm and below), physical verification tool familiarity
Technologies
Cadence Innovus, Cadence Genus, Synopsys ICC2, Synopsys Fusion Compiler, Synopsys PrimeTime, Calibre
Responsibilities
Execute block-level physical design from synthesized netlist to GDSII, drive timing convergence across MCMM scenarios, debug congestion and SI/crosstalk issues, contribute to methodology improvements through scripting
Seniority
Mid-level, hands-on IC