Principal, IC Digital Design Engineer
Core
Design high-performance digital ASICs for next-generation Ethernet and optical interconnects powering AI data centers, focusing on high-speed datapaths, DSP pipelines, and protocol handling.
Role type
Principal, IC Digital Design Engineer
Builds
Complex ASICs integrating DSP algorithms, protocol stacks, and PHY-level innovations for hyperscaler data infrastructure.
Domain
Semiconductor / High-speed Digital IC Design / Data Center Connectivity
Deliverable
production ML models | product features
Required skills
Digital ASIC design, Micro-architecture development, RTL implementation (SystemVerilog), High-performance DSP design, High-speed datapath design, Ethernet protocols, Front-end design flows (lint, CDC/RDC, synthesis, STA), Advanced process nodes (5nm/3nm), Debug skills (RTL simulation, emulation, FPGA, silicon bring-up)
Preferred skills
Advanced high-speed DSP algorithm implementation (adaptive equalization, channel estimation), FEC architectures (LDPC, RS, BCH), PHY design experience (PMA-level, SerDes-adjacent logic)
Responsibilities
Define SoC-level specifications and micro-architecture for complex subsystems; Develop synthesizable SystemVerilog RTL meeting performance/power targets; Drive full ASIC front-end design flow including timing closure and design-for-test; Lead integration of digital logic into top-level assemblies; Partner with DV teams on verification strategies and pre-silicon validation; Support post-silicon bring-up and debug; Contribute to design reviews and methodology improvements.
Seniority
Principal, hands-on IC with technical leadership
