DFT Engineer
Core
Design and integrate multiple chiplets into a System-in-package for high-speed CPU core designs.
Role type
Senior DFT Engineer (System-in-Package)
Builds
High-performance RISC-V CPU chips and multi-chiplet System-in-Package programs
Domain
Semiconductor / AI Hardware / CPU Design
Deliverable
production ML models | product features | infrastructure
Required skills
DFT planning, SoC-level silicon debug, formal verification, signoff of inserted DFT logic, scan chains, memory BIST, JTAG, ATPG, fault coverage reporting, TCL scripting, Python scripting
Preferred skills
cross-functional collaboration, risk assessment, resource planning
Technologies
Synopsys, Siemens, EDA tools
Responsibilities
Build and execute chip-level DFT strategies for high-speed CPU core designs and multi-chiplet System-in-Package programs. Implement and verify DFT features including scan chains, memory BIST, and JTAG to support manufacturing test and silicon debug. Partner with RTL, physical design, and verification teams to ensure testability throughout the design flow. Script, automate, and analyze DFT flows using industry-standard EDA tools, including ATPG and fault coverage reporting.
Seniority
Senior, hands-on IC
