Principal Physical Design Engineer
Core
Lead and execute Physical Design activities at block, sub-chip, and full-chip levels, driving implementation phases from floorplanning to signoff.
Role type
Principal Physical Design Engineer
Builds
Complex ASICs in leading edge technology
Domain
Semiconductor / VLSI Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production ML models (Incorrect mapping in thought, correcting to: physical/clinical work -> physical/clinical work is wrong. Correcting: physical/clinical work is not applicable. The deliverable is physical chips/ASICs. The schema options are fixed. Let's re-evaluate the schema options: 'production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work'. None fit perfectly. 'Infrastructure' is closest for hardware flow, but 'physical/clinical work' is specific. However, looking at the instruction 'Extract only facts stated explicitly... do NOT infer'. The text describes 'Physical Design'. The closest option in the fixed list is likely 'infrastructure' (as in design infrastructure) or it might be a trick. Wait, the schema says 'Deliverable: <one of: ...>'. I must choose one. Physical Design creates the layout for chips. This is 'infrastructure' in the sense of building the hardware foundation, or perhaps the schema is limited. Let's look at the options again. 'physical/clinical work' is definitely wrong. 'infrastructure' is the best fit for EDA flow and chip design among the choices provided, as it builds the underlying system.
Required skills
Floorplanning, Synthesis, Placement and optimization, Clock Tree Synthesis (CTS), Routing, Static Timing Analysis (STA), Physical Verification, Formal Equivalency, Power optimization, IR-drop analysis, Electromigration (EM) analysis, Technology node evaluation, IP selection, EDA tool selection
Preferred skills
Leading team to deliver planned PD goals, Methodology improvements, Automation development
Technologies
EDA tools, Custom clocking, Tapeout
Responsibilities
Lead and execute Physical Design activities at block, sub-chip, and full-chip levels; Contribute to Physical Design flow development, automation, and methodology improvements; Evaluate and recommend technology nodes, IP selection, EDA tools, and vendor solutions; Provide status updates on progress, risks, and mitigation plans; Drive all phases of implementation including Floorplanning, Synthesis, Placement, CTS, Routing, STA, Verification, and Power optimization.
Seniority
Principal, hands-on IC with leadership