Physical Design Engineer: Die-to-Die Interface (RTL to GDSII)
Core
Drive Die-to-Die (D2D) physical implementation from RTL to GDSII for multi-die/chiplet architectures in high-performance AI chips.
Role type
Senior ASIC Physical Design Engineer (D2D Interface)
Builds
High-speed D2D PHYs/controllers and full-chip implementations for AI platforms
Domain
Semiconductor / AI Hardware / Chiplet Architecture
Deliverable
production ML models
Required skills
Full-chip physical design flow, high-speed interface expertise (D2D, PCIe, HBM, SerDes), Static Timing Analysis (STA), Signal Integrity (SI) analysis, EDA tool expertise (Synopsys/Cadence/Mentor), automation scripting (Tcl, Python), advanced node tapeout experience (7nm or below)
Preferred skills
Analog PHY integration, power grid design, constraint-driven interface design
Technologies
Synopsys, Cadence, Mentor, Tcl, Python, LEF, LIB
Responsibilities
Lead D2D physical implementation and closure, own full PD flow (synthesis, floorplanning, P&R, CTS, sign-off), drive timing and verification (STA, SI, DRC/LVS), improve physical design methodologies and automation scripts, partner with full-chip and analog teams for tapeout requirements
Seniority
Senior, hands-on IC