ASIC Physical Design
1,421 open positions
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IP RTL Senior Design Engineer IntelIndia, Bangalore 2mo Develop high-quality intellectual property (IP) logic designs, register transfer level (RTL) coding, and simulations for Unified Intel Chassis designs, focusing on protocol bridges, access control, and reliability features.
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Senior Principal Engineer, Hardware Application Engineering - Board & System Design↗ I8is Inc.Santa Clara, CA, US $200k–$200k2mo Senior technical authority guiding complex board and system hardware designs for advanced networking and AI infrastructure platforms, ensuring optimization for performance, reliability, and high-volume production.
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Principal Technical Program Manager – DSP/Mixed-Signal ASIC Development – TeraWave BlueoriginSan Diego, CA $249k–$249k2mo Lead end-to-end development of advanced mixed-signal/DSP ASICs and SoCs (including Digital Beamforming) for TeraWave's satellite communication system, spanning architecture definition through production.
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Chip Design Engineer NVIDIAIsrael, Tel Aviv 2mo Design, implement, and verify next-generation high-speed Switch Silicon chips focusing on power, area, and performance.
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Staff Physical Design Engineer - SoC EMIR Engineer AsteralabsTel Aviv 2mo Backend power methodologies and EMIR analysis for high-performance SoCs in advanced FinFET nodes to ensure power robustness and reliability for AI clusters.
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HBM Logic Architect SkhynixamericaSan Jose, CA $150k–$150k2mo Establishing US-based HBM Architect Design team to address base-die architectural challenges in HBM and 3D-stacked DRAM for key customers.
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Senior Physical Design Engineer MicrosoftUnited States, Oregon, Hillsboro 2mo Own complete physical design execution for medium to large-size SOC blocks, driving end-to-end flow from synthesis through place-and-route and all signoff stages.
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PCB Layout Engineer TenstorrentSanta Clara $100k–$100k2mo Designing multi-layer PCB layouts for high-performance computing and AI hardware, ensuring signal integrity and manufacturability for mass production.
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Systems Architect AmbiqmicroincSingapore 2mo Define high-level architecture for Ambiq's low-power System-on-Chips (SoCs), focusing on subsystems and interfaces for audio, imaging, display, and high-speed links to enable ubiquitous AI at the edge.
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Staff Engineer, FPGA Design (R5347) ShieldaiSeattle, Washington 2mo Designing, implementing, verifying, and debugging FPGA-based solutions for complex avionics in Unmanned Aerial Vehicles (UAV).
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AI/ML driven ASIC Design and Implementation Automation Engineer NxpBangalore 2mo Develop prototype AI/ML solutions to improve efficiency and quality (power, performance, area, verification) for SoC and IP development flows.
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ASIC Design Engineer Technical Lead CiscoSan Jose, California, US $187k–$187k2mo Lead ASIC design for Cisco's core Switching, Routing, and Wireless products, defining architecture and implementing RTL to power AI-era hardware platforms.
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FPGA Lead/Architect/Implementor FlirDenmark - Kongens Lyngby 2mo Lead the architecture, design, and implementation of next-generation ultra-high-speed Ethernet test platforms supporting IEEE802.3dj and Ultra Ethernet standards.
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Sr Principal HW Design Engineer/HW Architect CadenceSAN JOSE $179k–$179k2mo Architect and design hardware system platforms for emulation-acceleration technologies, managing board-level design, schematic entry, PCB layout, and signal integrity.
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Hardware Engineer II ApconHeadquarters 2mo Designing physical electronics for network visibility and switching products, including embedded processors, switch ASICs, and high-speed digital circuitry.
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IC Digital Design Engineer AumovioBengaluru, KA, in 2mo Architect, design, and verify complex digital front-end circuits and systems for FPGA and ASIC implementations.
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ASIC Engineer, Architecture↗ MetaAustin, TX, US $114k–$114k2mo Define and drive architectural performance analysis, pre-silicon modeling, and microarchitectural exploration for custom ASICs powering Meta's AI and data center workloads.
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